mirror of https://github.com/VLSIDA/OpenRAM.git
PEP8 formatting
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69f5621245
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403ea17039
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@ -5,23 +5,18 @@
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import sys,re,shutil
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import copy
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import collections
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from design import design
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import debug
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import math
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import tech
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import random
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from .stimuli import *
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from .charutils import *
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import utils
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from globals import OPTS
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from .simulation import simulation
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# from .delay import delay
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import graph_util
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from sram_factory import factory
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class functional(simulation):
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"""
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Functions to write random data values to a random address then read them back and check
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@ -60,7 +55,6 @@ class functional(simulation):
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self.read_check = []
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self.read_results = []
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def run(self, feasible_period=None):
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if feasible_period: #period defaults to tech.py feasible period otherwise.
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self.period = feasible_period
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@ -282,14 +276,13 @@ class functional(simulation):
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# wmask must be reversed since a python list goes right to left and sram bits go left to right.
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return wmask[::-1]
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def gen_data(self):
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""" Generates a random word to write. """
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if not self.num_spare_cols:
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random_value = random.randint(0,(2**(self.word_size))-1)
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random_value = random.randint(0, (2 ** self.word_size) - 1)
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else:
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random_value1 = random.randint(0,(2**(self.word_size))-1)
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random_value2 = random.randint(0,(2**(self.num_spare_cols))-1)
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random_value1 = random.randint(0, (2 ** self.word_size) - 1)
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random_value2 = random.randint(0, (2 ** self.num_spare_cols) - 1)
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random_value = random_value1 + random_value2
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data_bits = self.convert_to_bin(random_value, False)
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return data_bits
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@ -504,7 +497,6 @@ class functional(simulation):
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cell_bl = cell_mod.get_bl_name(port)
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cell_br = cell_mod.get_br_name(port)
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bl_found = False
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# Only a single path should contain a single s_en name. Anything else is an error.
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bl_names = []
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exclude_set = self.get_bl_name_search_exclusions()
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