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Pgates are 8 M1 high by default. Port data is bitcell height.

This commit is contained in:
mrg 2020-01-30 03:34:04 +00:00
parent 0880c393fd
commit 400cf0333a
3 changed files with 30 additions and 25 deletions
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5
compiler/modules/hierarchical_decoder.py
View File

@ -21,7 +21,7 @@ class hierarchical_decoder(design.design):
""" """
Dynamically generated hierarchical decoder. Dynamically generated hierarchical decoder.
""" """
def __init__(self, name, rows, height=None): def __init__(self, name, rows):
design.design.__init__(self, name) design.design.__init__(self, name)
self.NAND_FORMAT = "DEC_NAND_{0}" self.NAND_FORMAT = "DEC_NAND_{0}"
@ -30,7 +30,8 @@ class hierarchical_decoder(design.design):
self.pre2x4_inst = [] self.pre2x4_inst = []
self.pre3x8_inst = [] self.pre3x8_inst = []
self.cell_height = height b = factory.create(module_type="bitcell")
self.cell_height = b.height
self.rows = rows self.rows = rows
self.num_inputs = math.ceil(math.log(self.rows, 2)) self.num_inputs = math.ceil(math.log(self.rows, 2))
(self.no_of_pre2x4,self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs) (self.no_of_pre2x4,self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs)

8
compiler/modules/wordline_driver.py
View File

@ -56,12 +56,16 @@ class wordline_driver(design.design):
self.add_pin("gnd", "GROUND") self.add_pin("gnd", "GROUND")
def add_modules(self): def add_modules(self):
b = factory.create(module_type="bitcell")
self.inv = factory.create(module_type="pdriver", self.inv = factory.create(module_type="pdriver",
fanout=self.cols, fanout=self.cols,
neg_polarity=True) neg_polarity=True,
height=b.height)
self.add_mod(self.inv) self.add_mod(self.inv)
self.nand2 = factory.create(module_type="pnand2") self.nand2 = factory.create(module_type="pnand2",
height=b.height)
self.add_mod(self.nand2) self.add_mod(self.nand2)
def route_vdd_gnd(self): def route_vdd_gnd(self):

42
compiler/pgates/pgate.py
View File

@ -27,8 +27,8 @@ class pgate(design.design):
if height: if height:
self.height = height self.height = height
elif not height: elif not height:
b = factory.create(module_type="bitcell") # By default, we make it 8 M1 pitch tall
self.height = b.height self.height = 8*self.m1_pitch
self.create_netlist() self.create_netlist()
if not OPTS.netlist_only: if not OPTS.netlist_only:
@ -128,37 +128,37 @@ class pgate(design.design):
# FIXME: float rounding problem # FIXME: float rounding problem
middle_position = middle_position.snap_to_grid() middle_position = middle_position.snap_to_grid()
# Add a rail width to extend the well to the top of the rail
nwell_max_offset = max(self.find_highest_layer_coords("nwell").y,
self.height + 0.5 * self.m1_width)
nwell_position = middle_position
nwell_height = nwell_max_offset - middle_position.y
if "nwell" in layer: if "nwell" in layer:
# Add a rail width to extend the well to the top of the rail
nwell_max_offset = max(self.find_highest_layer_coords("nwell").y,
self.height + 0.5 * self.m1_width)
nwell_position = middle_position
nwell_height = nwell_max_offset - middle_position.y
self.add_rect(layer="nwell", self.add_rect(layer="nwell",
offset=middle_position, offset=middle_position,
width=self.well_width, width=self.well_width,
height=nwell_height) height=nwell_height)
if "vtg" in layer: if "vtg" in layer:
self.add_rect(layer="vtg", self.add_rect(layer="vtg",
offset=nwell_position, offset=nwell_position,
width=self.well_width, width=self.well_width,
height=nwell_height) height=nwell_height)
# Start this half a rail width below the cell # Start this half a rail width below the cell
pwell_min_offset = min(self.find_lowest_layer_coords("pwell").y,
-0.5 * self.m1_width)
pwell_position = vector(0, pwell_min_offset)
pwell_height = middle_position.y - pwell_position.y
if "pwell" in layer: if "pwell" in layer:
pwell_min_offset = min(self.find_lowest_layer_coords("pwell").y,
-0.5 * self.m1_width)
pwell_position = vector(0, pwell_min_offset)
pwell_height = middle_position.y - pwell_position.y
self.add_rect(layer="pwell", self.add_rect(layer="pwell",
offset=pwell_position, offset=pwell_position,
width=self.well_width, width=self.well_width,
height=pwell_height) height=pwell_height)
if "vtg" in layer: if "vtg" in layer:
self.add_rect(layer="vtg", self.add_rect(layer="vtg",
offset=pwell_position, offset=pwell_position,
width=self.well_width, width=self.well_width,
height=pwell_height) height=pwell_height)
def add_nwell_contact(self, pmos, pmos_pos): def add_nwell_contact(self, pmos, pmos_pos):
""" Add an nwell contact next to the given pmos device. """ """ Add an nwell contact next to the given pmos device. """