Add port makeall for removing symmetry problems in netgen

compiler/verify/magic.py

@@ -53,6 +53,7 @@ def write_magic_script(cell_name, gds_name, extract=False, final_verification=Fa
     f.write("drc catchup\n")
     f.write("drc count total\n")
     f.write("drc count\n")
+    f.write("port makeall\n")
     if not extract:
         pre = "#"
     else:

technology/scn4m_subm/mag_lib/setup.tcl

@@ -4,12 +4,12 @@ equate class {-circuit1 nfet} {-circuit2 n}
 equate class {-circuit1 pfet} {-circuit2 p}
 # This circuit has symmetries and needs to be flattened to resolve them
 # or the banks won't pass
-flatten class {-circuit1 bitcell_array_0}
-flatten class {-circuit1 bitcell_array_1}
-flatten class {-circuit1 precharge_array_0}
-flatten class {-circuit1 precharge_array_1}
-flatten class {-circuit1 precharge_array_2}
-flatten class {-circuit1 precharge_array_3}
+#flatten class {-circuit1 bitcell_array_0}
+#flatten class {-circuit1 bitcell_array_1}
+#flatten class {-circuit1 precharge_array_0}
+#flatten class {-circuit1 precharge_array_1}
+#flatten class {-circuit1 precharge_array_2}
+#flatten class {-circuit1 precharge_array_3}
 property {-circuit1 nfet} remove as ad ps pd
 property {-circuit1 pfet} remove as ad ps pd
 property {-circuit2 n} remove as ad ps pd