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Add port makeall for removing symmetry problems in netgen

This commit is contained in:
Matt Guthaus 2019-02-22 17:10:23 -08:00 committed by Matt Guthaus
parent 2c01daae8d
commit 3ffcad0db8
2 changed files with 7 additions and 6 deletions
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1
compiler/verify/magic.py
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@ -53,6 +53,7 @@ def write_magic_script(cell_name, gds_name, extract=False, final_verification=Fa
f.write("drc catchup\n") f.write("drc catchup\n")
f.write("drc count total\n") f.write("drc count total\n")
f.write("drc count\n") f.write("drc count\n")
f.write("port makeall\n")
if not extract: if not extract:
pre = "#" pre = "#"
else: else:

12
technology/scn4m_subm/mag_lib/setup.tcl
View File

@ -4,12 +4,12 @@ equate class {-circuit1 nfet} {-circuit2 n}
equate class {-circuit1 pfet} {-circuit2 p} equate class {-circuit1 pfet} {-circuit2 p}
# This circuit has symmetries and needs to be flattened to resolve them # This circuit has symmetries and needs to be flattened to resolve them
# or the banks won't pass # or the banks won't pass
flatten class {-circuit1 bitcell_array_0} #flatten class {-circuit1 bitcell_array_0}
flatten class {-circuit1 bitcell_array_1} #flatten class {-circuit1 bitcell_array_1}
flatten class {-circuit1 precharge_array_0} #flatten class {-circuit1 precharge_array_0}
flatten class {-circuit1 precharge_array_1} #flatten class {-circuit1 precharge_array_1}
flatten class {-circuit1 precharge_array_2} #flatten class {-circuit1 precharge_array_2}
flatten class {-circuit1 precharge_array_3} #flatten class {-circuit1 precharge_array_3}
property {-circuit1 nfet} remove as ad ps pd property {-circuit1 nfet} remove as ad ps pd
property {-circuit1 pfet} remove as ad ps pd property {-circuit1 pfet} remove as ad ps pd
property {-circuit2 n} remove as ad ps pd property {-circuit2 n} remove as ad ps pd