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Change stages of delay to odd

This commit is contained in:
Matt Guthaus 2018-04-16 10:15:15 -07:00
parent 70c92c27ef
commit 3fe4578feb
1 changed files with 1 additions and 1 deletions
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2
compiler/modules/control_logic.py
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@ -73,7 +73,7 @@ class control_logic(design.design):
c = reload(__import__(OPTS.replica_bitline)) c = reload(__import__(OPTS.replica_bitline))
replica_bitline = getattr(c, OPTS.replica_bitline) replica_bitline = getattr(c, OPTS.replica_bitline)
# FIXME: These should be tuned according to the size! # FIXME: These should be tuned according to the size!
delay_stages = 4 # This should be even so that the delay line is inverting! delay_stages = 3 # Should be odd due to bug Kevin found
delay_fanout = 3 delay_fanout = 3
bitcell_loads = int(math.ceil(self.num_rows / 5.0)) bitcell_loads = int(math.ceil(self.num_rows / 5.0))
self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads) self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads)