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added DRC/LVS error count to datasheet

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This commit is contained in:
Jesse Cirimelli-Low
2018-11-01 14:02:33 -07:00
parent ce5001e0af
commit 3fa1d5522e
2 changed files with 33 additions and 17 deletions
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compiler/base/hierarchy_design.py
+19 -6
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@@ -6,6 +6,8 @@ import debug
import os
from globals import OPTS
total_drc_errors = 0
total_lvs_errors = 0
class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
"""
@@ -13,7 +15,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
Class consisting of a set of modules and instances of these modules
"""
name_map = []
def __init__(self, name):
try:
@@ -28,8 +29,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
self.name = name
hierarchy_layout.layout.__init__(self, name)
hierarchy_spice.spice.__init__(self, name)
# Check if the name already exists, if so, give an error
# because each reference must be a unique name.
# These modules ensure unique names or have no changes if they
@@ -70,12 +71,18 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
# Unit tests will check themselves.
# Do not run if disabled in options.
if not OPTS.is_unit_test and OPTS.check_lvsdrc:
global total_drc_errors
global total_lvs_errors
tempspice = OPTS.openram_temp + "/temp.sp"
tempgds = OPTS.openram_temp + "/temp.gds"
self.sp_write(tempspice)
self.gds_write(tempgds)
debug.check(verify.run_drc(self.name, tempgds) == 0,"DRC failed for {0}".format(self.name))
debug.check(verify.run_lvs(self.name, tempgds, tempspice, final_verification) == 0,"LVS failed for {0}".format(self.name))
num_drc_errors = verify.run_drc(self.name, tempgds)
num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification)
debug.check(num_drc_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_drc_errors))
debug.check(num_lvs_errors == 0,"LVS failed for {0} with {1} errors(s)".format(self.name,num_lvs_errors))
total_drc_errors += num_drc_errors
total_lvs_errors += num_lvs_errors
os.remove(tempspice)
os.remove(tempgds)
@@ -84,9 +91,12 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
# Unit tests will check themselves.
# Do not run if disabled in options.
if not OPTS.is_unit_test and OPTS.check_lvsdrc:
global total_drc_errors
tempgds = OPTS.openram_temp + "/temp.gds"
self.gds_write(tempgds)
debug.check(verify.run_drc(self.name, tempgds) == 0,"DRC failed for {0}".format(self.name))
num_errors = verify.run_drc(self.name, tempgds)
total_drc_errors += num_errors
debug.check(num_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_error))
os.remove(tempgds)
def LVS(self, final_verification=False):
@@ -94,11 +104,14 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
# Unit tests will check themselves.
# Do not run if disabled in options.
if not OPTS.is_unit_test and OPTS.check_lvsdrc:
global total_lvs_errors
tempspice = OPTS.openram_temp + "/temp.sp"
tempgds = OPTS.openram_temp + "/temp.gds"
self.sp_write(tempspice)
self.gds_write(tempgds)
debug.check(verify.run_lvs(self.name, tempgds, tempspice, final_verification) == 0,"LVS failed for {0}".format(self.name))
num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification)
total_lvs_errors += num_errors
debug.check(num_errors == 0,"LVS failed for {0} with {1} error(s)".format(self.name,num_errors))
os.remove(tempspice)
os.remove(tempgds)