mirror of https://github.com/VLSIDA/OpenRAM.git
fix column decoder
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@ -21,6 +21,7 @@ class hierarchical_predecode(design.design):
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self.number_of_inputs = input_number
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b = factory.create(module_type="bitcell")
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if not height:
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self.cell_height = b.height
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self.column_decoder = False
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