luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Specify two stage wl_en driver to prevent race condition

This commit is contained in:
mrg 2021-09-03 12:52:17 -07:00
parent 3e9cce0400
commit 3f031a90db
1 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
compiler/modules/control_logic.py
View File

@ -121,8 +121,10 @@ class control_logic(design.design):
# max_fanout = max(self.num_rows, self.num_cols) # max_fanout = max(self.num_rows, self.num_cols)
# wl_en drives every row in the bank # wl_en drives every row in the bank
# MRG 9/3/2021: Ensure that this is two stages to prevent race conditions with the write driver
size_list = [max(int(self.num_rows / 9), 1), max(int(self.num_rows / 3), 1)]
self.wl_en_driver = factory.create(module_type="pdriver", self.wl_en_driver = factory.create(module_type="pdriver",
fanout=self.num_rows, size_list=size_list,
height=dff_height) height=dff_height)
self.add_mod(self.wl_en_driver) self.add_mod(self.wl_en_driver)