first commit

change one sram into several single macros

compiler/gdsMill/gdsMill/vlsiLayout.py

@@ -742,6 +742,9 @@ class VlsiLayout:
         Search for a pin label and return ALL the enclosing rectangles on the same layer
         as the pin label.
         """
+        #debug
+        for pin in self.pins:
+            print(pin)
         shape_list = []
         pin_map = self.pins[pin_name]
         for pin_list in pin_map:

compiler/router/signal_escape_router.py

@@ -10,7 +10,7 @@ from openram import OPTS
 from .graph import graph
 from .graph_shape import graph_shape
 from .router import router
-
+import re
 
 class signal_escape_router(router):
     """
@@ -76,6 +76,8 @@ class signal_escape_router(router):
             self.find_vias(new_vias)
             routed_count += 1
             debug.info(2, "Routed {} of {} signal pins".format(routed_count, routed_max))
+            print("route pins:")
+            print(source)
         self.replace_layout_pins()
 
 
@@ -175,14 +177,18 @@ class signal_escape_router(router):
                               rect=rect,
                               layer_name_pp=layer)
             self.fake_pins.append(pin)
-
+            print("this is add_per")
+            print(pin.name)
+            print(pin.center)
 
     def create_fake_pin(self, pin):
         """ Create a fake pin on the perimeter orthogonal to the given pin. """
 
         ll, ur = self.bbox
         c = pin.center()
-
+        print("inside pin name")
+        print("----------------------------------------------------------")
+        print(pin.name)
         # Find the closest edge
         edge, vertical = self.get_closest_edge(c)
 
@@ -196,16 +202,62 @@ class signal_escape_router(router):
             fake_center = vector(ur.x + self.track_wire * 2, c.y)
         if edge == "top":
             fake_center = vector(c.x, ur.y + self.track_wire * 2)
+            #fake_center = vector(ll.x - self.track_wire * 2, c.y) # test if here we could change the pin position at the layout
 
+        # relocate the pin position
+        """
+        pattern = r'^addr0_1'
+        if re.match(pattern, pin.name):
+            vertical = True
+            fake_center = vector(ll.x - self.track_wire * 2, c.y + self.track_wire * 4)# fix still do not know how to control the distance between every fake pin
+            #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y?
+        pattern = r'^addr0_2'
+        if re.match(pattern, pin.name):
+            vertical = True
+            fake_center = vector(ll.x - self.track_wire * 2, c.y + self.track_wire * 8)# fix still do not know how to control the distance between every fake pin
+            #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y?
+        pattern = r'^addr0_3'
+        if re.match(pattern, pin.name):
+            vertical = True
+            fake_center = vector(ll.x - self.track_wire * 2, c.y + self.track_wire*12)# fix still do not know how to control the distance between every fake pin
+            #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y?
+        pattern = r'^addr0_4'
+        if re.match(pattern, pin.name):
+            vertical = True
+            fake_center = vector(ll.x - self.track_wire * 2, c.y + self.track_wire*16)# fix still do not know how to control the distance between every fake pin
+            #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y?
+        pattern = r'^p_en_bar0'
+        if re.match(pattern, pin.name):
+            vertical = True
+            fake_center = vector(ll.x - self.track_wire * 2, c.y)# fix still do not know how to control the distance between every fake pin
+            #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y?
+        pattern = r'^s_en0'
+        if re.match(pattern, pin.name):
+            vertical = True
+            fake_center = vector(ll.x - self.track_wire * 2, c.y + self.track_width *3)# fix still do not know how to control the distance between every fake pin
+            #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y?
+        pattern = r'^w_en0'
+        if re.match(pattern, pin.name):
+            vertical = True
+            fake_center = vector(ll.x - self.track_wire * 2, c.y + self.track_width * 6)# fix still do not know how to control the distance between every fake pin
+            #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y?
+        """
         # Create the fake pin shape
         layer = self.get_layer(int(not vertical))
         half_wire_vector = vector([self.half_wire] * 2)
         nll = fake_center - half_wire_vector
         nur = fake_center + half_wire_vector
+        #not test jet
+        #half_wire_vector = vector([self.half_wire] * 2)# out *2 means vector([self.half_wire, self.half_wire])
+        #nll = fake_center - half_wire_vector - half_wire_vector
+        #nur = fake_center + half_wire_vector + half_wire_vector
         rect = [nll, nur]
         pin = graph_shape(name="fake",
                           rect=rect,
                           layer_name_pp=layer)
+        print("this create_fake_pin")
+        print(pin.name)
+        print(pin.center)
         return pin
 
 
@@ -214,6 +266,8 @@ class signal_escape_router(router):
 
         to_route = []
         for name in pin_names:
+            print("==============the pin names===================")
+            print(name)
             pin = next(iter(self.pins[name]))
             fake = self.create_fake_pin(pin)
             to_route.append((pin, fake, pin.distance(fake)))

compiler/router/supply_router.py

@@ -76,6 +76,8 @@ class supply_router(router):
                 # Create the graph
                 g = graph(self)
                 g.create_graph(source, target)
+                # debug
+                debug.warning("graph creat success!")
                 # Find the shortest path from source to target
                 path = g.find_shortest_path()
                 # If no path is found, throw an error

compiler/sram.py

@@ -50,7 +50,7 @@ class sram():
         self.name = name
 
         from openram.modules.sram_1bank import sram_1bank as sram
-
+        #from openram.modules.sram_new import sram_1bank as sram
         self.s = sram(name, sram_config)
 
         self.s.create_netlist()

compiler/sram_road.py

@@ -0,0 +1,253 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+# This file generate sram part, aiming at using openroad to do the P&R
+import os
+import shutil
+import datetime
+from openram import debug
+from openram import sram_config as config
+from openram import OPTS, print_time
+
+
+class sram():
+    """
+    This is not a design module, but contains an SRAM design instance.
+    It could later try options of number of banks and organization to compare
+    results.
+    We can later add visualizer and other high-level functions as needed.
+    """
+    def __init__(self, sram_config=None, name=None):
+
+        # Create default configs if custom config isn't provided
+        if sram_config is None:
+            sram_config = config(word_size=OPTS.word_size,
+                                 num_words=OPTS.num_words,
+                                 write_size=OPTS.write_size,
+                                 num_banks=OPTS.num_banks,
+                                 words_per_row=OPTS.words_per_row,
+                                 num_spare_rows=OPTS.num_spare_rows,
+                                 num_spare_cols=OPTS.num_spare_cols)
+
+        if name is None:
+            name = OPTS.output_name
+
+        sram_config.set_local_config(self)
+
+        # reset the static duplicate name checker for unit tests
+        # in case we create more than one SRAM
+        from openram.base import design
+        design.name_map=[]
+
+        debug.info(2, "create sram of size {0} with {1} num of words {2} banks".format(self.word_size,
+                                                                                       self.num_words,
+                                                                                       self.num_banks))
+        start_time = datetime.datetime.now()
+
+        self.name = name
+
+        #from openram.modules.sram_1bank import sram_1bank as sram
+        from openram.modules.sram_part import sram_1bank as sram
+        self.s = sram(name, sram_config)
+
+    def get_sp_name(self):
+        if OPTS.use_pex:
+            # Use the extracted spice file
+            return self.pex_name
+        else:
+            # Use generated spice file for characterization
+            return self.sp_name
+
+    def sp_write(self, name, lvs=False, trim=False):
+        self.s.sp_write(name, lvs, trim)
+
+    def lef_write(self, name):
+        self.s.lef_write(name)
+
+    def gds_write(self, name):
+        self.s.gds_write(name)
+
+    def verilog_write(self, name):
+        self.s.verilog_write(name)
+        if self.num_banks != 1:
+            from openram.modules.sram_multibank import sram_multibank
+            mb = sram_multibank(self.s)
+            mb.verilog_write(name[:-2] + '_top.v')
+
+    def extended_config_write(self, name):
+        """Dump config file with all options.
+           Include defaults and anything changed by input config."""
+        f = open(name, "w")
+        var_dict = dict((name, getattr(OPTS, name)) for name in dir(OPTS) if not name.startswith('__') and not callable(getattr(OPTS, name)))
+        for var_name, var_value in var_dict.items():
+            if isinstance(var_value, str):
+                f.write(str(var_name) + " = " + "\"" + str(var_value) + "\"\n")
+            else:
+                f.write(str(var_name) + " = " + str(var_value)+ "\n")
+        f.close()
+        
+    def generate_files(self, module_name):
+        """use to generate gds, lef files for one certain layout"""
+        # Import this at the last minute so that the proper tech file
+        # is loaded and the right tools are selected
+        from openram import verify
+        from openram.characterizer import functional
+        from openram.characterizer import delay
+        
+        # Save the spice file
+        start_time = datetime.datetime.now()
+        spname = OPTS.output_path + self.s.name + module_name + ".sp"
+        debug.print_raw("SP: Writing to {0}".format(spname))
+        self.sp_write(spname)
+
+        print_time("Spice writing", datetime.datetime.now(), start_time)
+
+        # Save trimmed spice file
+        temp_trim_sp = "{0}trimmed_{1}.sp".format(OPTS.output_path, module_name)
+        self.sp_write(temp_trim_sp, lvs=False, trim=True)
+
+        if not OPTS.netlist_only:
+            # Write the layout
+            start_time = datetime.datetime.now()
+            gdsname = OPTS.output_path + self.s.name + module_name + ".gds"
+            debug.print_raw("GDS: Writing to {0}".format(gdsname))
+            self.gds_write(gdsname)
+            if OPTS.check_lvsdrc:
+                verify.write_drc_script(cell_name=self.s.name + module_name,
+                                        gds_name=os.path.basename(gdsname),
+                                        extract=True,
+                                        final_verification=True,
+                                        output_path=OPTS.output_path)
+            print_time("GDS", datetime.datetime.now(), start_time)
+
+            # Create a LEF physical model
+            start_time = datetime.datetime.now()
+            lefname = OPTS.output_path + self.s.name + module_name + ".lef"
+            debug.print_raw("LEF: Writing to {0}".format(lefname))
+            self.lef_write(lefname)
+            print_time("LEF", datetime.datetime.now(), start_time)
+
+        # Save the LVS file
+        start_time = datetime.datetime.now()
+        lvsname = OPTS.output_path + self.s.name + module_name + ".lvs.sp"
+        debug.print_raw("LVS: Writing to {0}".format(lvsname))
+        self.sp_write(lvsname, lvs=True)
+        if not OPTS.netlist_only and OPTS.check_lvsdrc:
+            verify.write_lvs_script(cell_name=self.s.name + module_name,
+                                    gds_name=os.path.basename(gdsname),
+                                    sp_name=os.path.basename(lvsname),
+                                    final_verification=True,
+                                    output_path=OPTS.output_path)
+        print_time("LVS writing", datetime.datetime.now(), start_time)
+
+        # Save the extracted spice file
+        if OPTS.use_pex:
+            start_time = datetime.datetime.now()
+            # Output the extracted design if requested
+            pexname = OPTS.output_path + self.s.name + module_name + ".pex.sp"
+            spname = OPTS.output_path + self.s.name + module_name + ".sp"
+            verify.run_pex(self.s.name, gdsname, spname, output=pexname)
+            sp_file = pexname
+            print_time("Extraction", datetime.datetime.now(), start_time)
+        else:
+            # Use generated spice file for characterization
+            sp_file = spname
+
+        # Write the config file
+        start_time = datetime.datetime.now()
+        try:
+            from shutil import copyfile
+            copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py')
+        except shutil.SameFileError:
+            pass
+        debug.print_raw("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
+        print_time("Config", datetime.datetime.now(), start_time)
+
+
+        # Write a verilog model
+        start_time = datetime.datetime.now()
+        vname = OPTS.output_path + self.s.name + '.v'
+        debug.print_raw("Verilog: Writing to {0}".format(vname))
+        self.verilog_write(vname)
+        print_time("Verilog", datetime.datetime.now(), start_time)
+
+        # Write out options if specified
+        if OPTS.output_extended_config:
+            start_time = datetime.datetime.now()
+            oname = OPTS.output_path + OPTS.output_name + "_extended.py"
+            debug.print_raw("Extended Config: Writing to {0}".format(oname))
+            self.extended_config_write(oname)
+            print_time("Extended Config", datetime.datetime.now(), start_time)
+        
+         
+    def save(self):
+        """ Save all the output files while reporting time to do it as well. """ 
+        for i in range(7):
+            if i == 0:
+                self.s.create_netlist_bank()
+                if not OPTS.netlist_only:
+                    self.s.create_layout_bank_only()
+                self.generate_files("bank")
+            elif i == 1:
+                self.s.create_netlist_control()
+                if not OPTS.netlist_only:
+                    for port in self.s.all_ports:
+                        self.s.create_layout_control_only(self, instance_index=port)
+                        self.generate_files("control_" + port)
+                else:
+                    for port in self.s.all_ports:
+                        self.generate_files("control_" + port)
+            elif i == 2:
+                self.s.create_netlist_row_addr_dff()
+                if not OPTS.netlist_only:
+                    for port in self.s.all_ports:
+                        self.s.create_layout_row_addr_dff_only(self, instance_index=port)
+                        self.generate_files("row_addr_dff_" + port)
+                else: 
+                    for port in self.s.all_ports:
+                        self.generate_files("row_addr_dff_" + port)
+            elif i == 3:    
+                if self.s.create_netlist_col_addr_dff() == False: 
+                    continue # do not need col addr dff
+                elif not OPTS.netlist_only:
+                    for port in self.s.all_ports:
+                        self.create_layout_col_addr_dff_only(self, instance_index=port)
+                        self.generate_files("col_addr_dff_" + port)
+                else:
+                    self.generate_files("col_addr_dff_" + port)
+            elif i == 4:     
+                self.s.create_netlist_data_dff()   
+                if not OPTS.netlist_only:
+                    for port in self.s.all_ports:
+                        self.s.create_layout_data_dff_only(self, instance_index=port)
+                        self.generate_files("data_dff_" + port)
+                else:
+                    for port in self.s.all_ports:
+                        self.generate_files("data_dff_" + port)
+            elif i == 5:
+                if self.s.create_netlist_wmask_dff() == False:
+                    continue # do not need wmask dff
+                elif not OPTS.netlist_only:
+                    for port in self.s.all_ports:
+                        self.s.create_layout_wmask_dff_only(self, instance_index=port)
+                        self.generate_files("wmask_dff_" + port)
+                else: 
+                    for port in self.s.all_ports:
+                        self.generate_files("wmask_dff_" + port)
+            elif i == 6:   
+                if self.s.create_netlist_spare_wen_dff() == False:
+                    continue # do not need spare wen dff 
+                elif not OPTS.netlist_only:
+                    for port in self.s.all_ports:
+                        self.s.create_layout_spare_wen_dff_only(self, instance_index=port) 
+                        self.generate_files("spare_wen_dff_" + port)    
+                else:
+                    for port in self.s.all_ports:
+                        self.generate_files("spare_wen_dff_" + port)
+
+                
+                

sram_compiler.py

@@ -69,9 +69,10 @@ for path in output_files:
     debug.print_raw(path)
 
 # Create an SRAM (we can also pass sram_config, see documentation/tutorials for details)
-from openram import sram
+#from openram import sram
-s = sram()
+#s = sram()
-
+from openram import sram_road
+s = sram_road.sram()
 # Output the files for the resulting SRAM
 s.save()