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https://github.com/VLSIDA/OpenRAM.git
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Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error.
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@@ -0,0 +1,69 @@
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#!/usr/bin/env python2.7
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"""
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Run a regresion test on various srams
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"""
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import unittest
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from testutils import header
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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import debug
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import calibre
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OPTS = globals.get_opts()
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class bank_test(unittest.TestCase):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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# we will manually run lvs/drc
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OPTS.check_lvsdrc = False
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import bank
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debug.info(1, "No column mux")
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a = bank.bank(word_size=4, num_words=16, words_per_row=1, num_banks=4, name="test_sram1")
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self.local_check(a)
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debug.info(1, "Two way column mux")
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a = bank.bank(word_size=4, num_words=32, words_per_row=2, num_banks=4, name="test_sram2")
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self.local_check(a)
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debug.info(1, "Four way column mux")
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a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=4, name="test_sram3")
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self.local_check(a)
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# Eight way has a short circuit of one column mux select to gnd rail
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# debug.info(1, "Eight way column mux")
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# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=2, name="test_sram4")
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# self.local_check(a)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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def local_check(self, a):
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tempspice = OPTS.openram_temp + "temp.sp"
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tempgds = OPTS.openram_temp + "temp.gds"
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a.sp_write(tempspice)
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a.gds_write(tempgds)
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self.assertFalse(calibre.run_drc(a.name, tempgds))
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self.assertFalse(calibre.run_lvs(a.name, tempgds, tempspice))
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os.remove(tempspice)
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os.remove(tempgds)
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# reset the static duplicate name checker for unit tests
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import design
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design.design.name_map=[]
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@@ -0,0 +1,69 @@
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#!/usr/bin/env python2.7
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"""
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Run a regresion test on various srams
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"""
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import unittest
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from testutils import header
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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import debug
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import calibre
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OPTS = globals.get_opts()
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class bank_test(unittest.TestCase):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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# we will manually run lvs/drc
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OPTS.check_lvsdrc = False
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import bank
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debug.info(1, "No column mux")
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a = bank.bank(word_size=4, num_words=16, words_per_row=1, num_banks=2, name="test_sram1")
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self.local_check(a)
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debug.info(1, "Two way column mux")
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a = bank.bank(word_size=4, num_words=32, words_per_row=2, num_banks=2, name="test_sram2")
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self.local_check(a)
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debug.info(1, "Four way column mux")
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a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=2, name="test_sram3")
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self.local_check(a)
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# Eight way has a short circuit of one column mux select to gnd rail
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# debug.info(1, "Eight way column mux")
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# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=2, name="test_sram4")
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# self.local_check(a)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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def local_check(self, a):
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tempspice = OPTS.openram_temp + "temp.sp"
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tempgds = OPTS.openram_temp + "temp.gds"
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a.sp_write(tempspice)
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a.gds_write(tempgds)
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self.assertFalse(calibre.run_drc(a.name, tempgds))
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self.assertFalse(calibre.run_lvs(a.name, tempgds, tempspice))
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os.remove(tempspice)
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os.remove(tempgds)
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# reset the static duplicate name checker for unit tests
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import design
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design.design.name_map=[]
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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