Clean up. Split class into own file.

compiler/base/hierarchy_spice.py

@@ -28,6 +28,7 @@ class spice():
     def __init__(self, name):
         self.name = name
 
+        self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
         # Holds subckts/mods for this module
         self.mods = []  
         # Holds the pins for this module
@@ -64,16 +65,20 @@ class spice():
         """ Adds a pin to the pins list. Default type is INOUT signal. """
         self.pins.append(name)
         self.pin_type[name]=pin_type
+        debug.check(pin_type in self.valid_signal_types, "Invalid signaltype for {0}: {1}".format(name,pin_type))
 
-    def add_pin_list(self, pin_list, pin_type_list="INOUT"):
+    def add_pin_list(self, pin_list, pin_type="INOUT"):
         """ Adds a pin_list to the pins list """
         # The type list can be a single type for all pins
         # or a list that is the same length as the pin list.
-        if type(pin_type_list)==str:
+        if type(pin_type)==str:
             for pin in pin_list:
-                self.add_pin(pin,pin_type_list)
+                debug.check(pin_type in self.valid_signal_types, "Invalid signaltype for {0}: {1}".format(pin,pin_type))
-        elif len(pin_type_list)==len(pin_list):
+                self.add_pin(pin,pin_type)
-            for (pin,ptype) in zip(pin_list, pin_type_list):
+                
+        elif len(pin_type)==len(pin_list):
+            for (pin,ptype) in zip(pin_list, pin_type):
+                debug.check(ptype in self.valid_signal_types, "Invalid signaltype for {0}: {1}".format(pin,ptype))
                 self.add_pin(pin,ptype)
         else:
             debug.error("Mismatch in type and pin list lengths.", -1)
@@ -91,7 +96,9 @@ class spice():
             
     def get_pin_type(self, name):
         """ Returns the type of the signal pin. """
-        return self.pin_type[name]
+        pin_type = self.pin_type[name]
+        debug.check(pin_type in self.valid_signal_types, "Invalid signaltype for {0}: {1}".format(name,pin_type))
+        return pin_type
 
     def get_pin_dir(self, name):
         """ Returns the direction of the pin. (Supply/ground are INOUT). """

compiler/characterizer/bit_polarity.py

@@ -0,0 +1,14 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+
+from enum import Enum
+
+class bit_polarity(Enum):
+    NONINVERTING = 0
+    INVERTING = 1
+    

compiler/characterizer/charutils.py

@@ -8,17 +8,7 @@
 import re
 import debug
 from globals import OPTS
-from enum import Enum
 
-class sram_op(Enum):
-    READ_ZERO = 0
-    READ_ONE = 1
-    WRITE_ZERO = 2
-    WRITE_ONE = 3
-    
-class bit_polarity(Enum):
-    NONINVERTING = 0
-    INVERTING = 1
     
 def relative_compare(value1,value2,error_tolerance=0.001):
     """ This is used to compare relative values for convergence. """

compiler/characterizer/delay.py

@@ -12,6 +12,8 @@ import math
 from .stimuli import *
 from .trim_spice import *
 from .charutils import *
+from .sram_op import *
+from .bit_polarity import *
 import utils
 from globals import OPTS
 from .simulation import simulation
@@ -21,7 +23,8 @@ import graph_util
 from sram_factory import factory
 
 class delay(simulation):
-    """Functions to measure the delay and power of an SRAM at a given address and
+    """
+    Functions to measure the delay and power of an SRAM at a given address and
     data bit.
 
     In general, this will perform the following actions:
@@ -40,7 +43,6 @@ class delay(simulation):
     def __init__(self, sram, spfile, corner):
         simulation.__init__(self, sram, spfile, corner)
 
-        # These are the member variables for a simulation
         self.targ_read_ports = []
         self.targ_write_ports = []
         self.period = 0
@@ -51,7 +53,7 @@ class delay(simulation):
         
     def create_measurement_names(self):
         """Create measurement names. The names themselves currently define the type of measurement"""
-        #Altering the names will crash the characterizer. TODO: object orientated approach to the measurements.
+
         self.delay_meas_names = ["delay_lh", "delay_hl", "slew_lh", "slew_hl"]
         self.power_meas_names = ["read0_power", "read1_power", "write0_power", "write1_power"]
         # self.voltage_when_names = ["volt_bl", "volt_br"]
@@ -114,11 +116,13 @@ class delay(simulation):
         return read_measures
     
     def create_bitline_measurement_objects(self):
-        """Create the measurements used for bitline delay values. Due to unique error checking, these are separated from other measurements.
+        """
-           These measurements are only associated with read values
+        Create the measurements used for bitline delay values. Due to
+        unique error checking, these are separated from other measurements.
+        These measurements are only associated with read values.
         """
         self.bitline_volt_meas = []
-        #Bitline voltage measures
+
         self.bitline_volt_meas.append(voltage_at_measure("v_bl_READ_ZERO", 
                                                          self.bl_name))
         self.bitline_volt_meas[-1].meta_str = sram_op.READ_ZERO
@@ -734,13 +738,13 @@ class delay(simulation):
             if type(val) != float:
                 continue
 
-            if meas.meta_str == sram_op.READ_ONE and val < self.vdd_voltage*.1:
+            if meas.meta_str == sram_op.READ_ONE and val < self.vdd_voltage*0.1:
                 success = False
-                debug.info(1, "Debug measurement failed. Value {}v was read on read 1 cycle.".format(val))
+                debug.info(1, "Debug measurement failed. Value {}V was read on read 1 cycle.".format(val))
                 bl_check = self.check_bitline_meas(bl_vals[sram_op.READ_ONE], br_vals[sram_op.READ_ONE])
-            elif meas.meta_str == sram_op.READ_ZERO and val > self.vdd_voltage*.9:
+            elif meas.meta_str == sram_op.READ_ZERO and val > self.vdd_voltage*0.9:
                 success = False
-                debug.info(1, "Debug measurement failed. Value {}v was read on read 0 cycle.".format(val))
+                debug.info(1, "Debug measurement failed. Value {}V was read on read 0 cycle.".format(val))
                 bl_check = self.check_bitline_meas(br_vals[sram_op.READ_ONE], bl_vals[sram_op.READ_ONE])
                 
             # If the bitlines have a correct value while the output does not then that is a 
@@ -1133,9 +1137,11 @@ class delay(simulation):
         self.measure_cycles = [{} for port in self.all_ports]
         
     def create_test_cycles(self):
-        """Returns a list of key time-points [ns] of the waveform (each rising edge)
+        """
+        Returns a list of key time-points [ns] of the waveform (each rising edge)
         of the cycles to do a timing evaluation. The last time is the end of the simulation
-        and does not need a rising edge."""
+        and does not need a rising edge.
+        """
         # Using this requires setting at least one port to target for simulation.
         if len(self.targ_write_ports) == 0 and len(self.targ_read_ports) == 0:
             debug.error("No port selected for characterization.",1)

compiler/characterizer/sram_op.py

@@ -0,0 +1,15 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+
+from enum import Enum
+
+class sram_op(Enum):
+    READ_ZERO = 0
+    READ_ONE = 1
+    WRITE_ZERO = 2
+    WRITE_ONE = 3

compiler/modules/bank.py

@@ -77,14 +77,14 @@ class bank(design.design):
         """ Adding pins for Bank module"""
         for port in self.read_ports:
             for bit in range(self.word_size):
-                self.add_pin("dout{0}_{1}".format(port,bit),"OUT")
+                self.add_pin("dout{0}_{1}".format(port,bit),"OUTPUT")
         for port in self.read_ports:
-            self.add_pin(self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]),"OUT")
+            self.add_pin(self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]),"OUTPUT")
         for port in self.read_ports:
-            self.add_pin(self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port]),"IN")
+            self.add_pin(self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port]),"INPUT")
         for port in self.write_ports:
             for bit in range(self.word_size):
-                self.add_pin("din{0}_{1}".format(port,bit),"IN")
+                self.add_pin("din{0}_{1}".format(port,bit),"INPUT")
         # if (self.word_size != self.write_size):
         #     for bit in range(self.word_size):
         #         self.add_pin()

compiler/options.py

@@ -84,7 +84,7 @@ class options(optparse.Values):
     # This determines whether LVS and DRC is checked for every submodule.
     inline_lvsdrc = False
     # Remove noncritical memory cells for characterization speed-up
-    trim_netlist = True
+    trim_netlist = False
     # Run with extracted parasitics
     use_pex = False