mirror of https://github.com/VLSIDA/OpenRAM.git
Respect the bus spacing parameter in predecoder.
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mrg
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aa5e1fd168
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@ -85,7 +85,6 @@ class hierarchical_predecode(design.design):
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self.bus_layer = layer_props.hierarchical_predecode.bus_layer
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self.bus_directions = layer_props.hierarchical_predecode.bus_directions
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if self.column_decoder:
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# Column decoders may be routed on M2/M3 if there's a write mask
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self.bus_pitch = self.m3_pitch
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@ -119,7 +118,8 @@ class hierarchical_predecode(design.design):
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self.input_rails = self.create_vertical_bus(layer=self.bus_layer,
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offset=offset,
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names=input_names,
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length=self.height - 2 * self.bus_pitch)
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length=self.height - 2 * self.bus_pitch,
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pitch=self.bus_pitch)
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invert_names = ["Abar_{}".format(x) for x in range(self.number_of_inputs)]
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non_invert_names = ["A_{}".format(x) for x in range(self.number_of_inputs)]
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@ -128,7 +128,8 @@ class hierarchical_predecode(design.design):
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self.decode_rails = self.create_vertical_bus(layer=self.bus_layer,
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offset=offset,
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names=decode_names,
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length=self.height - 2 * self.bus_pitch)
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length=self.height - 2 * self.bus_pitch,
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pitch=self.bus_pitch)
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def create_input_inverters(self):
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""" Create the input inverters to invert input signals for the decode stage. """
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@ -180,10 +181,12 @@ class hierarchical_predecode(design.design):
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mirror=mirror)
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def route(self):
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self.route_input_inverters()
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self.route_output_inverters()
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self.route_inputs_to_rails()
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self.route_and_to_rails()
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self.route_output_and()
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self.route_input_ands()
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self.route_output_ands()
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self.route_vdd_gnd()
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def route_inputs_to_rails(self):
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@ -215,7 +218,7 @@ class hierarchical_predecode(design.design):
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to_layer=self.bus_layer,
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offset=[self.decode_rails[a_pin].cx(), y_offset])
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def route_output_and(self):
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def route_output_ands(self):
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"""
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Route all conections of the outputs and gates
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"""
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@ -230,12 +233,40 @@ class hierarchical_predecode(design.design):
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def route_input_inverters(self):
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"""
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Route all conections of the inputs inverters [Inputs, outputs, vdd, gnd]
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Route all conections of the inverter inputs
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"""
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for inv_num in range(self.number_of_inputs):
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in_pin = "in_{}".format(inv_num)
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# route input
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pin = self.inv_inst[inv_num].get_pin("A")
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inv_in_pos = pin.center()
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in_pos = vector(self.input_rails[in_pin].cx(), inv_in_pos.y)
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self.add_path(self.input_layer, [in_pos, inv_in_pos])
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# Inverter input pin
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self.add_via_stack_center(from_layer=pin.layer,
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to_layer=self.input_layer,
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offset=inv_in_pos)
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# Input rail pin position
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via=self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=in_pos,
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directions=self.bus_directions)
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# Create the input pin at this location on the rail
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self.add_layout_pin_rect_center(text=in_pin,
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layer=self.bus_layer,
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offset=in_pos,
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height=via.mod.second_layer_height,
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width=via.mod.second_layer_width)
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def route_output_inverters(self):
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"""
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Route all conections of the inverter outputs
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"""
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for inv_num in range(self.number_of_inputs):
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out_pin = "Abar_{}".format(inv_num)
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in_pin = "in_{}".format(inv_num)
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inv_out_pin = self.inv_inst[inv_num].get_pin("Z")
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# add output so that it is just below the vdd or gnd rail
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@ -255,31 +286,11 @@ class hierarchical_predecode(design.design):
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offset=rail_pos,
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directions=self.bus_directions)
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# route input
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pin = self.inv_inst[inv_num].get_pin("A")
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inv_in_pos = pin.center()
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in_pos = vector(self.input_rails[in_pin].cx(), inv_in_pos.y)
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self.add_path(self.input_layer, [in_pos, inv_in_pos])
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self.add_via_stack_center(from_layer=pin.layer,
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to_layer=self.input_layer,
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offset=inv_in_pos)
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via=self.add_via_stack_center(from_layer=self.input_layer,
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to_layer=self.bus_layer,
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offset=in_pos)
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# Create the input pin at this location on the rail
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self.add_layout_pin_rect_center(text=in_pin,
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layer=self.bus_layer,
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offset=in_pos,
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height=via.mod.second_layer_height,
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width=via.mod.second_layer_width)
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def route_input_ands(self):
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"""
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Route the different permutations of the NAND/AND decocer cells.
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"""
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# This is a hack to fix via-to-via spacing issues, but it is currently
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# causing its own DRC problems.
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# if layer_props.hierarchical_predecode.vertical_supply:
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# below_rail = vector(self.decode_rails[out_pin].cx(), y_offset - (self.cell_height / 2))
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# self.add_path(self.bus_layer, [rail_pos, below_rail], width=self.li_width + self.m1_enclose_mcon * 2)
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def route_and_to_rails(self):
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# This 2D array defines the connection mapping
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and_input_line_combination = self.get_and_input_line_combination()
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for k in range(self.number_of_outputs):
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