Merge branch 'dev' into spmodels

compiler/characterizer/lib.py

@@ -44,20 +44,15 @@ class lib:
     def prepare_tables(self):
         """ Determine the load/slews if they aren't specified in the config file. """
         # These are the parameters to determine the table sizes
-        #self.load_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8])
+        self.load_scales = np.array(OPTS.load_scales)
-        self.load_scales = np.array([0.25, 1, 4])
-        #self.load_scales = np.array([0.25, 1])
         self.load = tech.spice["dff_in_cap"]
-        self.loads = self.load_scales*self.load
+        self.loads = self.load_scales * self.load
-        debug.info(1,"Loads: {0}".format(self.loads))
+        debug.info(1, "Loads: {0}".format(self.loads))
         
-        #self.slew_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8])
+        self.slew_scales = np.array(OPTS.slew_scales)
-        self.slew_scales = np.array([0.25, 1, 8])        
+        self.slew = tech.spice["rise_time"]
-        #self.slew_scales = np.array([0.25, 1])
+        self.slews = self.slew_scales * self.slew
-        self.slew = tech.spice["rise_time"]        
+        debug.info(1, "Slews: {0}".format(self.slews))
-        self.slews = self.slew_scales*self.slew
-        debug.info(1,"Slews: {0}".format(self.slews))
-
         
     def create_corners(self):
         """ Create corners for characterization. """
@@ -136,18 +131,18 @@ class lib:
 
         self.write_header()
         
-        #Loop over all ports. 
+        # Loop over all ports. 
         for port in self.all_ports:
-            #set the read and write port as inputs.
+            # set the read and write port as inputs.
             self.write_data_bus(port)
             self.write_addr_bus(port)
-            if self.sram.write_size:
+            if self.sram.write_size and port in self.write_ports:
                 self.write_wmask_bus(port)
-            self.write_control_pins(port) #need to split this into sram and port control signals
+            # need to split this into sram and port control signals
+            self.write_control_pins(port)
             self.write_clk_timing_power(port)
 
         self.write_footer()
-
         
     def write_footer(self):
         """ Write the footer """

compiler/example_configs/example_config_freepdk45.py

@@ -7,8 +7,11 @@ process_corners = ["TT"]
 supply_voltages = [1.0]
 temperatures = [25]
 
-route_supplies = True
+route_supplies = False
 check_lvsdrc = True
+# nominal_corners_only = True
+load_scales = [0.5, 1, 4]
+slew_scales = [0.5, 1]
 
 output_path = "temp"
 output_name = "sram_{0}_{1}_{2}".format(word_size,

compiler/globals.py

@@ -459,17 +459,27 @@ def set_default_corner():
             OPTS.process_corners = ["TT"]
         else:
             OPTS.process_corners = tech.spice["fet_models"].keys()
+            
     if (OPTS.supply_voltages == ""):
         if OPTS.nominal_corner_only:
             OPTS.supply_voltages = [tech.spice["supply_voltages"][1]]
         else:
             OPTS.supply_voltages = tech.spice["supply_voltages"]
+            
     if (OPTS.temperatures == ""):
         if OPTS.nominal_corner_only:
             OPTS.temperatures = [tech.spice["temperatures"][1]]
         else:
             OPTS.temperatures = tech.spice["temperatures"]
-    
+
+    # Load scales are fanout multiples of the DFF input cap
+    if (OPTS.load_scales == ""):
+        OPTS.load_scales = [0.25, 1, 4]
+
+    # Load scales are fanout multiples of the default spice input slew
+    if (OPTS.slew_scales == ""):
+        OPTS.slew_scales = [0.25, 1, 8]
+            
     
 def import_tech():
     """ Dynamically adds the tech directory to the path and imports it. """

compiler/options.py

@@ -42,6 +42,8 @@ class options(optparse.Values):
     supply_voltages = ""
     temperatures = ""
     process_corners = ""
+    load_scales = ""
+    slew_scales = ""
 
     # Size parameters must be specified by user in config file.
     # num_words = 0