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Merge branch 'dev' into spmodels

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This commit is contained in:
mrg
2020-10-19 14:49:07 -07:00
parent 804814d18d 7da3653ce5
commit 3d5c73709b
4 changed files with 29 additions and 19 deletions
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compiler/characterizer/lib.py
+12 -17
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@@ -44,20 +44,15 @@ class lib:
def prepare_tables(self):
""" Determine the load/slews if they aren't specified in the config file. """
# These are the parameters to determine the table sizes
#self.load_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8])
self.load_scales = np.array([0.25, 1, 4])
#self.load_scales = np.array([0.25, 1])
self.load_scales = np.array(OPTS.load_scales)
self.load = tech.spice["dff_in_cap"]
self.loads = self.load_scales*self.load
debug.info(1,"Loads: {0}".format(self.loads))
self.loads = self.load_scales * self.load
debug.info(1, "Loads: {0}".format(self.loads))
#self.slew_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8])
self.slew_scales = np.array([0.25, 1, 8])
#self.slew_scales = np.array([0.25, 1])
self.slew = tech.spice["rise_time"]
self.slews = self.slew_scales*self.slew
debug.info(1,"Slews: {0}".format(self.slews))
self.slew_scales = np.array(OPTS.slew_scales)
self.slew = tech.spice["rise_time"]
self.slews = self.slew_scales * self.slew
debug.info(1, "Slews: {0}".format(self.slews))
def create_corners(self):
""" Create corners for characterization. """
@@ -136,18 +131,18 @@ class lib:
self.write_header()
#Loop over all ports.
# Loop over all ports.
for port in self.all_ports:
#set the read and write port as inputs.
# set the read and write port as inputs.
self.write_data_bus(port)
self.write_addr_bus(port)
if self.sram.write_size:
if self.sram.write_size and port in self.write_ports:
self.write_wmask_bus(port)
self.write_control_pins(port) #need to split this into sram and port control signals
# need to split this into sram and port control signals
self.write_control_pins(port)
self.write_clk_timing_power(port)
self.write_footer()
def write_footer(self):
""" Write the footer """