mirror of https://github.com/VLSIDA/OpenRAM.git
freepdk45 col_mux fix
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@ -108,7 +108,7 @@ class single_level_column_mux(pgate.pgate):
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# This aligns it directly above the other tx with gates abutting
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nmos_upper_position = nmos_lower_position \
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+ vector(0, self.nmos.active_height + self.active_space)
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+ vector(0, self.nmos.active_height + max(self.active_space,self.poly_space))
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self.nmos_upper = self.add_inst(name="mux_tx2",
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mod=self.nmos,
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offset=nmos_upper_position)
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@ -117,10 +117,14 @@ class single_level_column_mux(pgate.pgate):
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def connect_poly(self):
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""" Connect the poly gate of the two pass transistors """
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# offset is the top of the lower nmos' diffusion
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# height is the distance between the nmos' diffusions, which depends on max(self.active_space,self.poly_space)
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offset = self.nmos_lower.get_pin("G").ul() - vector(0,self.poly_extend_active)
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height = self.nmos_upper.get_pin("G").by() + self.poly_extend_active - offset.y
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self.add_layout_pin(text="sel",
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layer="poly",
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offset=self.nmos_lower.get_pin("G").ul() - vector(0,self.poly_extend_active),
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height=self.active_space)
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offset=offset,
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height=height)
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def connect_bitlines(self):
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""" Connect the bitlines to the mux transistors """
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