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Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.

This commit is contained in:
Matt Guthaus 2018-11-05 10:59:08 -08:00
parent ce94366a1d
commit 3c5dc70ede
6 changed files with 48 additions and 28 deletions
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15
technology/freepdk45/sp_lib/cell_6t.sp vendored
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@ -1,10 +1,15 @@
.SUBCKT cell_6t bl br wl vdd gnd .SUBCKT cell_6t bl br wl vdd gnd
* Inverter 1
MM0 Qbar Q gnd gnd NMOS_VTG W=205.00n L=50n
MM4 Qbar Q vdd vdd PMOS_VTG W=90n L=50n
* Inverer 2
MM1 Q Qbar gnd gnd NMOS_VTG W=205.00n L=50n
MM5 Q Qbar vdd vdd PMOS_VTG W=90n L=50n
* Access transistors
MM3 bl wl Q gnd NMOS_VTG W=135.00n L=50n MM3 bl wl Q gnd NMOS_VTG W=135.00n L=50n
MM2 br wl Qb gnd NMOS_VTG W=135.00n L=50n MM2 br wl Qbar gnd NMOS_VTG W=135.00n L=50n
MM1 Q Qb gnd gnd NMOS_VTG W=205.00n L=50n
MM0 Qb Q gnd gnd NMOS_VTG W=205.00n L=50n
MM5 Q Qb vdd vdd PMOS_VTG W=90n L=50n
MM4 Qb Q vdd vdd PMOS_VTG W=90n L=50n
.ENDS cell_6t .ENDS cell_6t

16
technology/freepdk45/sp_lib/replica_cell_6t.sp vendored
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@ -1,10 +1,16 @@
.SUBCKT replica_cell_6t bl br wl vdd gnd .SUBCKT replica_cell_6t bl br wl vdd gnd
* Inverter 1
MM4 Qbar gnd vdd vdd PMOS_VTG W=90n L=50n
MM0 Qbar gnd gnd gnd NMOS_VTG W=205.00n L=50n
* Inverter 2
MM5 gnd Qbar vdd vdd PMOS_VTG W=90n L=50n
MM1 gnd Qbar gnd gnd NMOS_VTG W=205.00n L=50n
* Access transistors
MM3 bl wl gnd gnd NMOS_VTG W=135.00n L=50n MM3 bl wl gnd gnd NMOS_VTG W=135.00n L=50n
MM2 br wl net4 gnd NMOS_VTG W=135.00n L=50n MM2 br wl Qbar gnd NMOS_VTG W=135.00n L=50n
MM1 gnd net4 gnd gnd NMOS_VTG W=205.00n L=50n
MM0 net4 gnd gnd gnd NMOS_VTG W=205.00n L=50n
MM5 gnd net4 vdd vdd PMOS_VTG W=90n L=50n
MM4 net4 gnd vdd vdd PMOS_VTG W=90n L=50n
.ENDS replica_cell_6t .ENDS replica_cell_6t

BIN
technology/scn4m_subm/gds_lib/replica_cell_6t.gds
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Binary file not shown.

8
technology/scn4m_subm/mag_lib/replica_cell_6t.mag
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@ -1,6 +1,6 @@
magic magic
tech scmos tech scmos
timestamp 1536091380 timestamp 1541443051
<< nwell >> << nwell >>
rect -8 29 42 51 rect -8 29 42 51
<< pwell >> << pwell >>
@ -76,15 +76,15 @@ rect 17 6 21 10
rect -2 44 15 48 rect -2 44 15 48
rect 19 44 32 48 rect 19 44 32 48
rect -2 40 2 44 rect -2 40 2 44
rect 22 40 26 44
rect 32 40 36 44 rect 32 40 36 44
rect 11 36 12 40 rect 11 36 12 40
rect 26 36 27 40 rect 26 36 27 40
rect -2 26 2 29 rect -2 26 2 29
rect 11 22 15 36 rect -2 16 2 22
rect 11 18 15 36
rect 23 24 27 36 rect 23 24 27 36
rect -2 18 15 22
rect 25 20 27 24 rect 25 20 27 24
rect -2 16 2 18
rect 14 14 15 18 rect 14 14 15 18
rect 23 18 27 20 rect 23 18 27 20
rect 32 26 36 29 rect 32 26 36 29

17
technology/scn4m_subm/sp_lib/cell_6t.sp vendored
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@ -3,11 +3,16 @@
.SUBCKT cell_6t bl br wl vdd gnd .SUBCKT cell_6t bl br wl vdd gnd
* SPICE3 file created from cell_6t.ext - technology: scmos * SPICE3 file created from cell_6t.ext - technology: scmos
M1000 a_36_40# a_28_32# vdd vdd p w=0.6u l=0.8u * Inverter 1
M1001 vdd a_36_40# a_28_32# vdd p w=0.6u l=0.8u M1000 Q Qbar vdd vdd p w=0.6u l=0.8u
M1002 a_36_40# a_28_32# gnd gnd n w=1.6u l=0.4u M1002 Q Qbar gnd gnd n w=1.6u l=0.4u
M1003 gnd a_36_40# a_28_32# gnd n w=1.6u l=0.4u
M1004 a_36_40# wl bl gnd n w=0.8u l=0.4u * Inverter 2
M1005 a_28_32# wl br gnd n w=0.8u l=0.4u M1001 vdd Q Qbar vdd p w=0.6u l=0.8u
M1003 gnd Q Qbar gnd n w=1.6u l=0.4u
* Access transistors
M1004 Q wl bl gnd n w=0.8u l=0.4u
M1005 Qbar wl br gnd n w=0.8u l=0.4u
.ENDS .ENDS

20
technology/scn4m_subm/sp_lib/replica_cell_6t.sp vendored
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@ -1,14 +1,18 @@
*********************** "cell_6t" ****************************** *********************** "cell_6t" ******************************
.SUBCKT replica_cell_6t bl br wl vdd gnd .SUBCKT replica_cell_6t bl br wl vdd gnd
* SPICE3 file created from replica_cell_6t.ext - technology: scmos * SPICE3 file created from cell_6t.ext - technology: scmos
M1000 gnd a_28_32# vdd vdd p w=0.6u l=0.8u * Inverter 1
M1001 vdd gnd a_28_32# vdd p w=0.6u l=0.8u M1000 Q vdd vdd vdd p w=0.6u l=0.8u
** SOURCE/DRAIN TIED M1002 Q vdd gnd gnd n w=1.6u l=0.4u
M1002 gnd a_28_32# gnd gnd n w=1.6u l=0.4u
M1003 gnd gnd a_28_32# gnd n w=1.6u l=0.4u * Inverter 2
M1004 gnd wl bl gnd n w=0.8u l=0.4u M1001 vdd Q vdd vdd p w=0.6u l=0.8u
M1005 a_28_32# wl br gnd n w=0.8u l=0.4u M1003 gnd Q vdd gnd n w=1.6u l=0.4u
* Access transistors
M1004 Q wl bl gnd n w=0.8u l=0.4u
M1005 vdd wl br gnd n w=0.8u l=0.4u
.ENDS .ENDS