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Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
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+10
-5
@@ -1,10 +1,15 @@
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.SUBCKT cell_6t bl br wl vdd gnd
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* Inverter 1
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MM0 Qbar Q gnd gnd NMOS_VTG W=205.00n L=50n
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MM4 Qbar Q vdd vdd PMOS_VTG W=90n L=50n
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* Inverer 2
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MM1 Q Qbar gnd gnd NMOS_VTG W=205.00n L=50n
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MM5 Q Qbar vdd vdd PMOS_VTG W=90n L=50n
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* Access transistors
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MM3 bl wl Q gnd NMOS_VTG W=135.00n L=50n
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MM2 br wl Qb gnd NMOS_VTG W=135.00n L=50n
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MM1 Q Qb gnd gnd NMOS_VTG W=205.00n L=50n
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MM0 Qb Q gnd gnd NMOS_VTG W=205.00n L=50n
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MM5 Q Qb vdd vdd PMOS_VTG W=90n L=50n
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MM4 Qb Q vdd vdd PMOS_VTG W=90n L=50n
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MM2 br wl Qbar gnd NMOS_VTG W=135.00n L=50n
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.ENDS cell_6t
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+11
-5
@@ -1,10 +1,16 @@
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.SUBCKT replica_cell_6t bl br wl vdd gnd
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* Inverter 1
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MM4 Qbar gnd vdd vdd PMOS_VTG W=90n L=50n
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MM0 Qbar gnd gnd gnd NMOS_VTG W=205.00n L=50n
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* Inverter 2
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MM5 gnd Qbar vdd vdd PMOS_VTG W=90n L=50n
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MM1 gnd Qbar gnd gnd NMOS_VTG W=205.00n L=50n
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* Access transistors
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MM3 bl wl gnd gnd NMOS_VTG W=135.00n L=50n
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MM2 br wl net4 gnd NMOS_VTG W=135.00n L=50n
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MM1 gnd net4 gnd gnd NMOS_VTG W=205.00n L=50n
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MM0 net4 gnd gnd gnd NMOS_VTG W=205.00n L=50n
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MM5 gnd net4 vdd vdd PMOS_VTG W=90n L=50n
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MM4 net4 gnd vdd vdd PMOS_VTG W=90n L=50n
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MM2 br wl Qbar gnd NMOS_VTG W=135.00n L=50n
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.ENDS replica_cell_6t
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