Replaced analytical characterization with graph implementation. Removed most analytical delay functions used by old chacterizer.

compiler/modules/bank.py

@@ -976,40 +976,7 @@ class bank(design.design):
         self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos])
         self.add_via_center(layers=("metal1", "via1", "metal2"),
                             offset=control_pos)
-
-    def analytical_delay(self, corner, slew, load, port):
-        """ return  analytical delay of the bank. This will track the clock to output path"""
-        #FIXME: This delay is determined in the control logic. Should be moved here.
-        # word_driver_delay = self.wordline_driver.analytical_delay(corner, 
-                                                                  # slew, 
-                                                                  # self.bitcell_array.input_load())
-
-        #FIXME: Array delay is the same for every port.
-        word_driver_slew =  0
-        if self.words_per_row > 1:
-            bitline_ext_load = self.port_data[port].column_mux_array.get_drain_cin()
-        else:
-            bitline_ext_load = self.port_data[port].sense_amp_array.get_drain_cin()
-            
-        bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_slew, bitline_ext_load)
-
-        bitcell_array_slew = 0
-        #This also essentially creates the same delay for each port. Good structure, no substance
-        if self.words_per_row > 1:
-            sa_load = self.port_data[port].sense_amp_array.get_drain_cin()
-            column_mux_delay = self.port_data[port].column_mux_array.analytical_delay(corner, 
-                                                                                            bitcell_array_slew,
-                                                                                            sa_load)
-        else:
-            column_mux_delay = []  
-            
-        column_mux_slew =  0    
-        sense_amp_delay = self.port_data[port].sense_amp_array.analytical_delay(corner, 
-                                                                                      column_mux_slew,
-                                                                                      load)
-        # output load of bitcell_array is set to be only small part of bl for sense amp.
-        return  bitcell_array_delay + column_mux_delay + sense_amp_delay
-    
+ 
     def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True):    
         """Get the all the stage efforts for each stage in the path within the bank clk_buf to a wordline"""
         #Decoder is assumed to have settled before the negative edge of the clock. Delay model relies on this assumption

compiler/modules/bitcell_array.py

@@ -148,17 +148,7 @@ class bitcell_array(design.design):
                 for pin_name in ["vdd", "gnd"]:
                     for pin in inst.get_pins(pin_name):
                         self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer)
-    
-    def analytical_delay(self, corner, slew, load):
-        """Returns relative delay of the bitline in the bitcell array"""
-        from tech import parameter
-        #The load being driven/drained is mostly the bitline but could include the sense amp or the column mux.
-        #The load from the bitlines is due to the drain capacitances from all the other bitlines and wire parasitics.
-        drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
-        wire_unit_load = .05 * drain_load #Wires add 5% to this.
-        bitline_load = (drain_load+wire_unit_load)*self.row_size
-        return [self.cell.analytical_delay(corner, slew, load+bitline_load)]
-    
+
     def analytical_power(self, corner, load):
         """Power of Bitcell array and bitline in nW."""
         from tech import drc, parameter

compiler/modules/replica_bitcell_array.py

@@ -373,17 +373,7 @@ class replica_bitcell_array(design.design):
     def get_rbl_br_name(self, port):
         """ Return the BR for the given RBL port """
         return self.rbl_br_names[port]
-    
-    def analytical_delay(self, corner, slew, load):
-        """Returns relative delay of the bitline in the bitcell array"""
-        from tech import parameter
-        #The load being driven/drained is mostly the bitline but could include the sense amp or the column mux.
-        #The load from the bitlines is due to the drain capacitances from all the other bitlines and wire parasitics.
-        drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
-        wire_unit_load = 0.05 * drain_load #Wires add 5% to this.
-        bitline_load = (drain_load+wire_unit_load)*self.row_size
-        return [self.cell.analytical_delay(corner, slew, load+bitline_load)]
-    
+
     def analytical_power(self, corner, load):
         """Power of Bitcell array and bitline in nW."""
         from tech import drc, parameter

compiler/modules/sense_amp_array.py

@@ -144,10 +144,7 @@ class sense_amp_array(design.design):
 
     def input_load(self):
         return self.amp.input_load()
-    
-    def analytical_delay(self, corner, slew, load):
-        return [self.amp.analytical_delay(corner, slew=slew, load=load)]
-        
+      
     def get_en_cin(self):
         """Get the relative capacitance of all the sense amp enable connections in the array"""
         sense_amp_en_cin = self.amp.get_en_cin()

compiler/modules/single_level_column_mux_array.py

@@ -210,15 +210,6 @@ class single_level_column_mux_array(design.design):
                 self.add_via_center(layers=("metal1", "via1", "metal2"),
                                     offset=br_out_offset)
 
-       
-    def analytical_delay(self, corner, slew, load):
-        from tech import parameter
-        """Returns relative delay that the column mux adds"""
-        #Single level column mux will add parasitic loads from other mux pass transistors and the sense amp.
-        drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
-        array_load = drain_load*self.words_per_row
-        return [self.mux.analytical_delay(corner, slew, load+array_load)]
-        
     def get_drain_cin(self):
         """Get the relative capacitance of the drain of the NMOS pass TX"""
         from tech import parameter