luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-05 09:03:53 +02:00
Code Issues Packages Projects Releases Wiki Activity

Replaced analytical characterization with graph implementation. Removed most analytical delay functions used by old chacterizer.

Browse Source
This commit is contained in:
Hunter Nichols
2019-08-08 02:33:51 -07:00
parent fc1cba099c
commit 3c44ce2df6
7 changed files with 33 additions and 120 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/characterizer/delay.py
+28 -26
View File
@@ -1277,6 +1277,7 @@ class delay(simulation):
def sum_delays(self, delays):
"""Adds the delays (delay_data objects) so the correct slew is maintained"""
delay = delays[0]
for i in range(1, len(delays)):
delay+=delays[i]
@@ -1303,40 +1304,41 @@ class delay(simulation):
bl_name,br_name = self.get_bl_name(self.graph.all_paths, port)
bl_path = [path for path in self.graph.all_paths if bl_name in path][0]
# Set delay/power for slews and loads
port_data = self.get_empty_measure_data_dict()
power = self.analytical_power(slews, loads)
debug.info(1,'Slew, Load, Delay(ns), Slew(ns)')
max_delay = 0.0
for slew in slews:
for load in loads:
# Calculate delay based on slew and load
path_delays = self.graph.get_timing(bl_path, self.corner, slew, load)
total_delay = self.sum_delays(path_delays)
max_delay = max(max_delay, total_delay.delay)
debug.info(1,'{}, {}, {}, {}'.format(slew,load,total_delay.delay/1e3, total_delay.slew/1e3))
debug.error('Not finished with graph delay characterization.', 1)
# power = self.analytical_power(slews, loads)
# port_data = self.get_empty_measure_data_dict()
# relative_loads = [logical_effort.convert_farad_to_relative_c(c_farad) for c_farad in loads]
# for slew in slews:
# for load in relative_loads:
# self.set_load_slew(load,slew)
# bank_delay = self.sram.analytical_delay(self.corner, self.slew,self.load)
# for port in self.all_ports:
# for mname in self.delay_meas_names+self.power_meas_names:
# if "power" in mname:
# port_data[port][mname].append(power.dynamic)
# elif "delay" in mname:
# port_data[port][mname].append(bank_delay[port].delay/1e3)
# elif "slew" in mname:
# port_data[port][mname].append(bank_delay[port].slew/1e3)
# else:
# debug.error("Measurement name not recognized: {}".format(mname),1)
# period_margin = 0.1
# risefall_delay = bank_delay[self.read_ports[0]].delay/1e3
# sram_data = { "min_period":risefall_delay*2*period_margin,
# "leakage_power": power.leakage}
# debug.info(2,"SRAM Data:\n{}".format(sram_data))
# debug.info(2,"Port Data:\n{}".format(port_data))
return (sram_data,port_data)
# Delay is only calculated on a single port and replicated for now.
for port in self.all_ports:
for mname in self.delay_meas_names+self.power_meas_names:
if "power" in mname:
port_data[port][mname].append(power.dynamic)
elif "delay" in mname and port in self.read_ports:
port_data[port][mname].append(total_delay.delay/1e3)
elif "slew" in mname and port in self.read_ports:
port_data[port][mname].append(total_delay.slew/1e3)
else:
debug.error("Measurement name not recognized: {}".format(mname),1)
# Estimate the period as double the delay with margin
period_margin = 0.1
sram_data = { "min_period":(max_delay/1e3)*2*period_margin,
"leakage_power": power.leakage}
debug.info(2,"SRAM Data:\n{}".format(sram_data))
debug.info(2,"Port Data:\n{}".format(port_data))
return (sram_data,port_data)
def analytical_power(self, slews, loads):
"""Get the dynamic and leakage power from the SRAM"""