Consistents of bl x port then br x port

2026-09-03 00:29:02 +02:00 · 2020-09-09 13:38:13 -07:00
parent 3062aba214
commit 3c0707e5d1
2 changed files with 11 additions and 15 deletions
@@ -196,6 +196,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
        for bit in self.rbls:
            for port in self.all_ports:
                self.rbl_bitline_names[bit].append("rbl_bl_{0}_{1}".format(port, bit))
+            for port in self.all_ports:
                self.rbl_bitline_names[bit].append("rbl_br_{0}_{1}".format(port, bit))
        # Make a flat list too
        self.all_rbl_bitline_names = [x for sl in self.rbl_bitline_names for x in sl]