mirror of https://github.com/VLSIDA/OpenRAM.git
Add new power supplies to delay chain
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@ -601,6 +601,19 @@ class layout(lef.lef):
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width=xmax-xmin,
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width=xmax-xmin,
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height=ymax-ymin)
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height=ymax-ymin)
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def add_power_pin(self, name, loc):
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"""
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Add a single power pin from M3 own to M1
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"""
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=loc,
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rotate=90)
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=loc)
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self.add_layout_pin_rect_center(text=name,
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layer="metal3",
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offset=loc)
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def add_power_ring(self, bbox):
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def add_power_ring(self, bbox):
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"""
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"""
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Create vdd and gnd power rings around an area of the bounding box argument. Must
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Create vdd and gnd power rings around an area of the bounding box argument. Must
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@ -164,19 +164,17 @@ class delay_chain(design.design):
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""" Add vdd and gnd rails and the input/output. Connect the gnd rails internally on
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""" Add vdd and gnd rails and the input/output. Connect the gnd rails internally on
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the top end with no input/output to obstruct. """
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the top end with no input/output to obstruct. """
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for driver in self.driver_inst_list:
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for pin_name in ["vdd", "gnd"]:
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vdd_pin = driver.get_pin("vdd")
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for driver in self.driver_inst_list:
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self.add_layout_pin(text="vdd",
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pin = driver.get_pin(pin_name)
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layer="metal1",
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start = pin.lc()
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offset=vdd_pin.ll(),
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end = start + vector(self.width,0)
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width=self.width,
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self.add_power_pin(pin_name, start)
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height=vdd_pin.height())
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self.add_power_pin(pin_name, end)
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gnd_pin = driver.get_pin("gnd")
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self.add_rect(layer="metal1",
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self.add_layout_pin(text="gnd",
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offset=pin.ll(),
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layer="metal1",
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width=self.width,
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offset=gnd_pin.ll(),
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height=pin.height())
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width=self.width,
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height=gnd_pin.height())
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# input is A pin of first inverter
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# input is A pin of first inverter
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a_pin = self.driver_inst_list[0].get_pin("A")
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a_pin = self.driver_inst_list[0].get_pin("A")
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