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Fixed import errors with mux analytical delay model.

This commit is contained in:
Hunter Nichols 2018-10-26 17:37:25 -07:00
parent 98a00f985b
commit 3bb8aa7e55
2 changed files with 2 additions and 1 deletions
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1
compiler/modules/sense_amp.py
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@ -25,6 +25,7 @@ class sense_amp(design.design):
def input_load(self): def input_load(self):
#Input load for the bitlines which are connected to the source/drain of a TX. Not the selects. #Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
from tech import spice, parameter
bitline_pmos_size = 8 #FIXME: This should be set somewhere and referenced. Probably in tech file. bitline_pmos_size = 8 #FIXME: This should be set somewhere and referenced. Probably in tech file.
return spice["min_tx_drain_c"]*(bitline_pmos_size/parameter["min_tx_size"])#ff return spice["min_tx_drain_c"]*(bitline_pmos_size/parameter["min_tx_size"])#ff

2
compiler/modules/single_level_column_mux_array.py
View File

@ -218,7 +218,7 @@ class single_level_column_mux_array(design.design):
rotate=90) rotate=90)
def analytical_delay(self, vdd, slew, load=0.0): def analytical_delay(self, vdd, slew, load=0.0):
from tech import spice from tech import spice, parameter
r = spice["min_tx_r"]/(self.mux.ptx_width/parameter["min_tx_size"]) r = spice["min_tx_r"]/(self.mux.ptx_width/parameter["min_tx_size"])
#Drains of mux transistors make up capacitance. #Drains of mux transistors make up capacitance.
c_para = spice["min_tx_drain_c"]*(self.mux.ptx_width/parameter["min_tx_size"])*self.words_per_row#ff c_para = spice["min_tx_drain_c"]*(self.mux.ptx_width/parameter["min_tx_size"])*self.words_per_row#ff