sky130 rba passing :)

compiler/drc/custom_cell_properties.py

@@ -186,12 +186,15 @@ class cell_properties():
         self.names["col_cap_bitcell_2port"] = "col_cap_cell_2rw"
         self.names["row_cap_bitcell_1port"] = "row_cap_cell_1rw"
         self.names["row_cap_bitcell_2port"] = "row_cap_cell_2rw"
+        self.names["internal"] = "internal"
+
         self.use_strap = False
         self._ptx = _ptx(model_is_subckt=False,
                          bin_spice_models=False)
 
         self._pgate = _pgate(add_implants=False)
 
+
         self._inv_dec = cell(["A", "Z", "vdd", "gnd"],
                               ["INPUT", "OUTPUT", "POWER", "GROUND"])
 
@@ -230,6 +233,12 @@ class cell_properties():
 
         self._row_cap_2port = bitcell(["wl0", "wl1", "gnd"],
                                        ["INPUT", "INPUT", "POWER", "GROUND"])
+        
+        self._internal = cell([],[])
+
+    @property
+    def internal(self):
+        return self._internal
 
     @property
     def ptx(self):

compiler/modules/__init__.py

@@ -80,3 +80,4 @@ from .write_mask_and_array import *
 from .sram_1bank import *
 from .sram_config import *
 from .sram import *
+from .internal_base import *

compiler/modules/internal_base.py

@@ -0,0 +1,16 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+
+from base import design
+
+class internal_base(design):
+
+    def __init__(self, name, cell_name=None, prop=None):
+        design.__init__(self, name, cell_name, prop)
+ 
+