mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'dev' into supply_router
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commit
3a3ecb27d2
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@ -1362,8 +1362,9 @@ class delay(simulation):
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else:
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debug.error("Measurement name not recognized: {}".format(mname), 1)
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# Estimate the period as double the delay with margin
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period_margin = 0.1
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# Margin for error in period. Calculated by averaging required margin for a small and large
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# memory. FIXME: margin is quite large, should be looked into.
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period_margin = 1.85
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sram_data = {"min_period": (max_delay / 1e3) * 2 * period_margin,
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"leakage_power": power.leakage}
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@ -63,7 +63,9 @@ class model_delay_test(openram_test):
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# Only compare the delays
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spice_delays = {key:value for key, value in spice_data.items() if 'delay' in key}
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spice_delays['min_period'] = spice_data['min_period']
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model_delays = {key:value for key, value in model_data.items() if 'delay' in key}
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model_delays['min_period'] = model_data['min_period']
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debug.info(1,"Spice Delays={}".format(spice_delays))
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debug.info(1,"Model Delays={}".format(model_delays))
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