mirror of https://github.com/VLSIDA/OpenRAM.git
Undo extra space due to nwell spacing
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@ -191,7 +191,7 @@ class hierarchical_decoder(design.design):
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+ self.predecoder_width \
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+ self.predecoder_width \
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+ self.internal_routing_width \
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+ self.internal_routing_width \
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+ self.nand_width \
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+ self.nand_width \
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+ 2 * self.m1_pitch
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+ self.m1_space
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def route_inputs(self):
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def route_inputs(self):
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""" Create input bus for the predecoders """
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""" Create input bus for the predecoders """
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