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Use and2_dec instead of buf_dec for better wldriver layout

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mrg
2020-12-01 11:19:12 -08:00
parent b621c3bdc0
commit 3829213afe
2 changed files with 20 additions and 6 deletions
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compiler/modules/replica_bitcell_array.py
+3 -3
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@@ -121,18 +121,18 @@ class replica_bitcell_array(bitcell_base_array):
# the array.
# These go from the top (where the bitcell array starts ) down
replica_bit = self.rbl[0] - port
column_offset = self.rbl[0]
elif port in self.right_rbl:
# We will always have self.rbl[0] rows of replica wordlines below
# the array.
# These go from the bottom up
replica_bit = self.rbl[0] + self.row_size + port
column_offset = self.rbl[0] + self.column_size + 1
else:
continue
# If we have an odd numer on the bottom
column_offset = self.rbl[0] + 1
self.replica_columns[port] = factory.create(module_type="replica_column",
rows=self.row_size,
rbl=self.rbl,