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https://github.com/VLSIDA/OpenRAM.git
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Fail simulation tests if correct spice is not found. Correctly load spice characterizer.
This commit is contained in:
Matt Guthaus
@@ -0,0 +1,154 @@
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#!/usr/bin/env python2.7
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"Run a regresion test on a basic parameterized transistors"
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import unittest
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from testutils import header
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class ptx_test(unittest.TestCase):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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global verify
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import verify
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OPTS.check_lvsdrc = False
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import ptx
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import tech
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debug.info(2, "Checking three fingers PMOS")
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fet = ptx.ptx(width=tech.drc["minwidth_tx"],
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mults=4,
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tx_type="pmos",
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connect_active=True,
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connect_poly=True)
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self.local_check(fet)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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def add_mods(self, fet):
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self.create_contacts()
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self.add_well_extension(fet)
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self.add_wire_extension(fet)
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self.add_well_tiedown(fet)
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self.add_poly_tiedown(fet)
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def create_contacts(self):
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layer_stack = ("active", "contact", "metal1")
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self.well_contact = contact.contact(layer_stack)
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layer_stack = ("poly", "contact", "metal1")
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self.poly_contact = contact.contact(layer_stack)
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def add_well_tiedown(self, fet):
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offset = [fet.active_contact_positions[0][0],
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fet.active_contact_positions[0][1] + fet.well_height]
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fet.add_inst(name="well_tap",
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mod=self.well_contact,
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offset=offset,
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mirror="R0",
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rotate=0)
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fet.well_contact = self.well_contact
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fet.well_tiedown_location = offset
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def add_well_extension(self, fet):
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well_define = {"pmos": "nwell",
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"nmos": "pwell"}
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well_type = well_define[fet.tx_type]
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offset = getattr(fet,"{}_position".format(well_type))
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if tech.info["has_{0}".format(well_type)]:
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fet.add_rect(layerNumber=tech.layer[well_type],
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offset=offset,
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width=fet.well_width,
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height=2 * fet.well_height)
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fet.add_rect(layerNumber=tech.layer["{0}implant".format(fet.tx_type[0])],
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offset=offset,
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width=fet.well_width,
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height=2 * fet.well_height)
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fet.add_rect(layerNumber=tech.layer["vtg"],
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offset=offset,
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width=fet.well_width,
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height=2 * fet.well_height)
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well_type = "{0}well".format(fet.tx_type[0])
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offset[1] = offset[1] - 3 * fet.well_height
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if tech.info["has_{0}".format(well_type)]:
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fet.add_rect(layerNumber=tech.layer[well_type],
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offset=offset,
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width=fet.well_width,
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height=3 * fet.well_height)
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fet.add_rect(layerNumber=tech.layer["{0}implant".format(well_define[fet.tx_type][
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0])],
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offset=offset,
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width=fet.well_width,
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height=3 * fet.well_height)
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fet.add_rect(layerNumber=tech.layer["vtg"],
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offset=offset,
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width=fet.well_width,
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height=3 * fet.well_height)
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def add_wire_extension(self, fet):
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xcorrect = (fet.active_contact.width / 2) - (tech.drc["minwidth_metal1"] / 2)
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offset = [fet.active_contact_positions[0][0] + xcorrect,
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fet.active_contact_positions[0][1]]
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fet.add_rect(layerNumber=tech.layer["metal1"],
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offset=offset,
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width=tech.drc["minwidth_metal1"],
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height=fet.well_height)
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offset = [fet.active_contact_positions[-1][0] + xcorrect,
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fet.active_contact_positions[-1][1] - 2 * fet.well_height]
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fet.add_rect(layerNumber=tech.layer["metal1"],
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offset=offset,
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width=tech.drc["minwidth_metal1"],
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height=2 * fet.well_height)
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offset = [fet.poly_positions[-1][0],
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fet.poly_positions[-1][1] - (fet.well_height)]
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fet.add_rect(layerNumber=tech.layer["poly"],
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offset=offset,
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width=tech.drc["minwidth_poly"],
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height=fet.well_height)
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def add_poly_tiedown(self, fet):
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xcorrect = abs(self.poly_contact.upper_layer_vertical_enclosure -
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self.poly_contact.lower_layer_vertical_enclosure)
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offset = [fet.poly_positions[-1][0] - xcorrect,
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fet.poly_positions[-1][1] - (fet.well_height)]
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fet.add_inst(name="poly_contact",
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mod=self.poly_contact,
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offset=offset,
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mirror="R270")
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offset = [fet.active_contact_positions[-1][0], fet.active_contact_positions
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[-1][1] - 2 * fet.well_height - self.well_contact.height]
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fet.poly_tiedown_location = offset
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fet.add_inst(name="n_tiedown",
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mod=self.well_contact,
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offset=offset)
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tech.ptx_port.add_custom_layer(fet)
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def local_check(self, fet):
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tempspice = OPTS.openram_temp + "temp.sp"
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tempgds = OPTS.openram_temp + "temp.gds"
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fet.sp_write(tempspice)
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fet.gds_write(tempgds)
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self.assertFalse(verify.run_drc(fet.name, tempgds))
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os.remove(tempspice)
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os.remove(tempgds)
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@@ -18,12 +18,12 @@ class timing_sram_test(unittest.TestCase):
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OPTS.check_lvsdrc = False
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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self.assertTrue(OPTS.spice_exe)
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# This is a hack to reload the characterizer __init__ with the spice version
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import characterizer
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reload(characterizer)
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from characterizer import delay
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self.assertTrue(OPTS.spice_exe)
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import sram
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@@ -18,12 +18,12 @@ class timing_setup_test(unittest.TestCase):
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OPTS.check_lvsdrc = False
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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self.assertTrue(OPTS.spice_exe)
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# This is a hack to reload the characterizer __init__ with the spice version
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import characterizer
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reload(characterizer)
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from characterizer import setup_hold
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self.assertTrue(OPTS.spice_exe)
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import sram
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import tech
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@@ -18,12 +18,12 @@ class timing_sram_test(unittest.TestCase):
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OPTS.check_lvsdrc = False
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OPTS.spice_name="ngspice"
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OPTS.analytical_delay = False
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self.assertTrue(OPTS.spice_exe)
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# This is a hack to reload the characterizer __init__ with the spice version
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import characterizer
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reload(characterizer)
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from characterizer import delay
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self.assertTrue(OPTS.spice_exe)
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import sram
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@@ -18,12 +18,12 @@ class timing_setup_test(unittest.TestCase):
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OPTS.check_lvsdrc = False
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OPTS.spice_name="ngspice"
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OPTS.analytical_delay = False
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self.assertTrue(OPTS.spice_exe)
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# This is a hack to reload the characterizer __init__ with the spice version
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import characterizer
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reload(characterizer)
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from characterizer import setup_hold
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self.assertTrue(OPTS.spice_exe)
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import sram
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import tech
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@@ -0,0 +1,6 @@
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BSIM4: Berkeley Short Channel IGFET Model-4
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Developed by Xuemei (Jane) Xi, Jin He, Mohan Dunga, Prof. Ali Niknejad and Prof. Chenming Hu in 2003.
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++++++++++ BSIM4v4 PARAMETER CHECKING BELOW ++++++++++
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Warning: This model supports BSIM4.2.1, 4.3.0 and 4.4.0; you specified a wrong version number.
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Model = nmos_vtg
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@@ -0,0 +1,15 @@
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05_bitcell_array_test.py
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06_hierarchical_decoder_test.py
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06_hierarchical_predecode2x4_test.py
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06_hierarchical_predecode3x8_test.py
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07_single_level_column_mux_array_test.py
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08_precharge_array_test.py
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09_sense_amp_array_test.py
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10_write_driver_array_test.py
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11_ms_flop_array_test.py
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12_tri_gate_array_test.py
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13_delay_chain_test.py
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14_replica_bitline_test.py
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16_control_logic_test.py
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19_multi_bank_test.py
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19_single_bank_test.py
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