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Changed named on delay chain sizing variable. Automatic sizing default is False.

This commit is contained in:
Hunter Nichols 2020-11-17 14:29:01 -08:00
parent df4c2bad1f
commit 35e1a523cc
3 changed files with 3 additions and 4 deletions
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4
compiler/characterizer/model_check.py
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@ -412,7 +412,7 @@ class model_check(delay):
data_dict[self.bl_meas_name] = bl_delays[read_port] data_dict[self.bl_meas_name] = bl_delays[read_port]
data_dict[self.power_name] = powers[read_port] data_dict[self.power_name] = powers[read_port]
if not OPTS.use_tech_delay_chain_size: #Model is not used in this case if OPTS.auto_delay_chain_sizing: #Model is not used in this case
wl_model_delays, sae_model_delays = self.get_model_delays(read_port) wl_model_delays, sae_model_delays = self.get_model_delays(read_port)
debug.info(1,"Wordline model delays:\n\t {}".format(wl_model_delays)) debug.info(1,"Wordline model delays:\n\t {}".format(wl_model_delays))
debug.info(1,"SAE model delays:\n\t {}".format(sae_model_delays)) debug.info(1,"SAE model delays:\n\t {}".format(sae_model_delays))
@ -439,7 +439,7 @@ class model_check(delay):
name_dict[self.power_name] = self.power_meas_names name_dict[self.power_name] = self.power_meas_names
#name_dict[self.wl_slew_name] = self.wl_slew_meas_names #name_dict[self.wl_slew_name] = self.wl_slew_meas_names
if not OPTS.use_tech_delay_chain_size: if OPTS.auto_delay_chain_sizing:
name_dict[self.wl_model_name] = name_dict["wl_measures"] #model uses same names as measured. name_dict[self.wl_model_name] = name_dict["wl_measures"] #model uses same names as measured.
name_dict[self.sae_model_name] = name_dict["sae_measures"] name_dict[self.sae_model_name] = name_dict["sae_measures"]

2
compiler/options.py
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@ -60,7 +60,7 @@ class options(optparse.Values):
rbl_delay_percentage = 0.5 rbl_delay_percentage = 0.5
# Allow manual adjustment of the delay chain over automatic # Allow manual adjustment of the delay chain over automatic
use_tech_delay_chain_size = False auto_delay_chain_sizing = False
delay_chain_stages = 9 delay_chain_stages = 9
delay_chain_fanout_per_stage = 4 delay_chain_fanout_per_stage = 4

1
compiler/tests/21_hspice_delay_test.py
View File

@ -38,7 +38,6 @@ class timing_sram_test(openram_test):
# num_words=256, # num_words=256,
# num_banks=1) # num_banks=1)
# c.words_per_row=2 # c.words_per_row=2
# OPTS.use_tech_delay_chain_size = True
c.recompute_sizes() c.recompute_sizes()
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = factory.create(module_type="sram", sram_config=c) s = factory.create(module_type="sram", sram_config=c)