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Use internal pin names in path names for signal traces.

This commit is contained in:
mrg 2020-11-19 08:45:09 -08:00
parent fbed738b4a
commit 35c162acbd
2 changed files with 2 additions and 2 deletions
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2
compiler/base/hierarchy_layout.py
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@ -377,7 +377,7 @@ class layout():
""" """
Return a pin list of all pins Return a pin list of all pins
""" """
return self.pin_map.keys() return self.pins
def copy_layout_pin(self, instance, pin_name, new_name=""): def copy_layout_pin(self, instance, pin_name, new_name=""):
""" """

2
compiler/bitcells/bitcell_2port.py
View File

@ -91,7 +91,7 @@ class bitcell_2port(bitcell_base.bitcell_base):
def build_graph(self, graph, inst_name, port_nets): def build_graph(self, graph, inst_name, port_nets):
"""Adds edges to graph. Multiport bitcell timing graph is too complex """Adds edges to graph. Multiport bitcell timing graph is too complex
to use the add_graph_edges function.""" to use the add_graph_edges function."""
pin_dict = {pin: port for pin, port in zip(self.pin_names, port_nets)} pin_dict = {pin: port for pin, port in zip(self.get_original_pin_names(), port_nets)}
# Edges hardcoded here. Essentially wl->bl/br for both ports. # Edges hardcoded here. Essentially wl->bl/br for both ports.
# Port 0 edges # Port 0 edges
graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self) graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)