mirror of https://github.com/VLSIDA/OpenRAM.git
Remove 1rw_1r
This commit is contained in:
mrg
parent
cf63499e76
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3567a3e913
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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from tech import cell_properties as props
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import bitcell_base
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class bitcell_1rw_1r(bitcell_base.bitcell_base):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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pin_names = [props.bitcell.cell_1rw1r.pin.bl0,
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props.bitcell.cell_1rw1r.pin.br0,
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props.bitcell.cell_1rw1r.pin.bl1,
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props.bitcell.cell_1rw1r.pin.br1,
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props.bitcell.cell_1rw1r.pin.wl0,
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props.bitcell.cell_1rw1r.pin.wl1,
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props.bitcell.cell_1rw1r.pin.vdd,
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props.bitcell.cell_1rw1r.pin.gnd]
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type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
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"INPUT", "INPUT", "POWER", "GROUND"]
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storage_nets = ['Q', 'Q_bar']
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def __init__(self, name):
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super().__init__(name)
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debug.info(2, "Create bitcell with 1RW and 1R Port")
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self.nets_match = self.do_nets_exist(self.storage_nets)
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pin_names = self.pin_names
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self.bl_names = [pin_names[0], pin_names[2]]
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self.br_names = [pin_names[1], pin_names[3]]
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self.wl_names = [pin_names[4], pin_names[5]]
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def get_bitcell_pins(self, col, row):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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pin_name = props.bitcell.cell_1rw1r.pin
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bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col),
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"{0}_{1}".format(pin_name.br0, col),
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"{0}_{1}".format(pin_name.bl1, col),
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"{0}_{1}".format(pin_name.br1, col),
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"{0}_{1}".format(pin_name.wl0, row),
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"{0}_{1}".format(pin_name.wl1, row),
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"vdd",
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"gnd"]
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return bitcell_pins
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def get_all_wl_names(self):
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""" Creates a list of all wordline pin names """
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return [props.bitcell.cell_1rw1r.pin.wl0,
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props.bitcell.cell_1rw1r.pin.wl1]
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def get_all_bitline_names(self):
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""" Creates a list of all bitline pin names (both bl and br) """
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return [props.bitcell.cell_1rw1r.pin.bl0,
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props.bitcell.cell_1rw1r.pin.br0,
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props.bitcell.cell_1rw1r.pin.bl1,
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props.bitcell.cell_1rw1r.pin.br1]
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def get_all_bl_names(self):
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""" Creates a list of all bl pins names """
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return [props.bitcell.cell_1rw1r.pin.bl0,
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props.bitcell.cell_1rw1r.pin.bl1]
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def get_all_br_names(self):
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""" Creates a list of all br pins names """
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return [props.bitcell.cell_1rw1r.pin.br0,
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props.bitcell.cell_1rw1r.pin.br1]
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def get_read_bl_names(self):
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""" Creates a list of bl pin names associated with read ports """
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return [props.bitcell.cell_1rw1r.pin.bl0,
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props.bitcell.cell_1rw1r.pin.bl1]
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def get_read_br_names(self):
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""" Creates a list of br pin names associated with read ports """
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return [props.bitcell.cell_1rw1r.pin.br0,
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props.bitcell.cell_1rw1r.pin.br1]
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def get_write_bl_names(self):
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""" Creates a list of bl pin names associated with write ports """
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return [props.bitcell.cell_1rw1r.pin.bl0]
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def get_write_br_names(self):
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""" Creates a list of br pin names asscociated with write ports"""
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return [props.bitcell.cell_1rw1r.pin.br1]
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def get_bl_name(self, port=0):
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"""Get bl name by port"""
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debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
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return self.bl_names[port]
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def get_br_name(self, port=0):
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"""Get bl name by port"""
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debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
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return self.br_names[port]
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def get_wl_name(self, port=0):
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"""Get wl name by port"""
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debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
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return self.wl_names[port]
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges to graph. Multiport bitcell timing graph is too complex
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to use the add_graph_edges function."""
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pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
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# Edges hardcoded here. Essentially wl->bl/br for both ports.
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# Port 0 edges
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pins = props.bitcell.cell_1rw1r.pin
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graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self)
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graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self)
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# Port 1 edges
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graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self)
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graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self)
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@ -1,35 +0,0 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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from tech import cell_properties as props
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import bitcell_base
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class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base):
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"""
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A single bit cell which is forced to store a 0.
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This module implements the single memory cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library. """
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pin_names = [props.bitcell.cell_1rw1r.pin.bl0,
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props.bitcell.cell_1rw1r.pin.br0,
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props.bitcell.cell_1rw1r.pin.bl1,
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props.bitcell.cell_1rw1r.pin.br1,
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props.bitcell.cell_1rw1r.pin.wl0,
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props.bitcell.cell_1rw1r.pin.wl1,
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props.bitcell.cell_1rw1r.pin.vdd,
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props.bitcell.cell_1rw1r.pin.gnd]
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type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
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"INPUT", "INPUT", "POWER", "GROUND"]
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def __init__(self, name):
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super().__init__(name)
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debug.info(2, "Create dummy bitcell 1rw+1r object")
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@ -1,62 +0,0 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import bitcell_base
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from tech import cell_properties as props
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from tech import parameter, drc
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import logical_effort
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class replica_bitcell_1rw_1r(bitcell_base.bitcell_base):
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"""
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A single bit cell which is forced to store a 0.
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This module implements the single memory cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library. """
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pin_names = [props.bitcell.cell_1rw1r.pin.bl0,
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props.bitcell.cell_1rw1r.pin.br0,
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props.bitcell.cell_1rw1r.pin.bl1,
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props.bitcell.cell_1rw1r.pin.br1,
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props.bitcell.cell_1rw1r.pin.wl0,
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props.bitcell.cell_1rw1r.pin.wl1,
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props.bitcell.cell_1rw1r.pin.vdd,
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props.bitcell.cell_1rw1r.pin.gnd]
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type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
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def __init__(self, name):
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super().__init__(name)
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debug.info(2, "Create replica bitcell 1rw+1r object")
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def get_stage_effort(self, load):
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parasitic_delay = 1
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size = 0.5 # This accounts for bitline being drained thought the access TX and internal node
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cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
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read_port_load = 0.5 # min size NMOS gate load
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return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False)
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def input_load(self):
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"""Return the relative capacitance of the access transistor gates"""
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# FIXME: This applies to bitline capacitances as well.
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# FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
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access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"]
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return 2 * access_tx_cin
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges to graph. Multiport bitcell timing graph is too complex
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to use the add_graph_edges function."""
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pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
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pins = props.bitcell.cell_1rw1r.pin
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# Edges hardcoded here. Essentially wl->bl/br for both ports.
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# Port 0 edges
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graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self)
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graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self)
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# Port 1 edges
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graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self)
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graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self)
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