mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-30 01:48:33 +02:00
Adding simulation.py for common functions between functional and delay tests. Updating functional test.
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@@ -32,14 +32,14 @@ class psram_func_test(openram_test):
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from sram import sram
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from sram_config import sram_config
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c = sram_config(word_size=2,
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num_words=16,
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c = sram_config(word_size=4,
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num_words=32,
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num_banks=1)
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c.words_per_row=1
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c.words_per_row=2
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 2
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OPTS.num_r_ports = 2
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OPTS.num_r_ports = 4
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debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank. Multiport with {}RW {}W {}R.".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports))
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s = sram(c, name="sram1")
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@@ -49,10 +49,9 @@ class psram_func_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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(fail,error) = f.multiport_run()
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(success,error) = f.multiport_run()
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if fail:
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print(error)
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self.assertTrue(not success,error)
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globals.end_openram()
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@@ -30,9 +30,9 @@ class sram_func_test(openram_test):
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from sram import sram
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from sram_config import sram_config
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c = sram_config(word_size=4,
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num_words=16,
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num_words=32,
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num_banks=1)
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c.words_per_row=1
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c.words_per_row=2
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debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank")
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s = sram(c, name="sram1")
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@@ -41,10 +41,9 @@ class sram_func_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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(fail, error) = f.run()
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(success, error) = f.run()
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if fail:
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print(error)
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self.assertTrue(not success,error)
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globals.end_openram()
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@@ -0,0 +1,63 @@
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#!/usr/bin/env python3
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"""
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Run a regression test on various srams
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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#@unittest.skip("SKIPPING 22_psram_func_test")
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class psram_func_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.spice_name="ngspice"
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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from characterizer import functional
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if not OPTS.spice_exe:
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debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
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from sram import sram
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from sram_config import sram_config
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c = sram_config(word_size=4,
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num_words=32,
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num_banks=1)
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c.words_per_row=2
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 2
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OPTS.num_r_ports = 4
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debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank. Multiport with {}RW {}W {}R.".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports))
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s = sram(c, name="sram1")
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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(success,error) = f.multiport_run()
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self.assertTrue(not success,error)
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globals.end_openram()
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# instantiate a copdsay of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@@ -0,0 +1,55 @@
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#!/usr/bin/env python3
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"""
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Run a regression test on various srams
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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#@unittest.skip("SKIPPING 22_sram_func_test")
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class sram_func_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.spice_name="ngspice"
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OPTS.analytical_delay = False
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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from characterizer import functional
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if not OPTS.spice_exe:
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debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
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from sram import sram
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from sram_config import sram_config
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c = sram_config(word_size=4,
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num_words=32,
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num_banks=1)
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c.words_per_row=2
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debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank")
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s = sram(c, name="sram1")
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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(success, error) = f.run()
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self.assertTrue(not success,error)
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globals.end_openram()
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# instantiate a copdsay of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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