Adding simulation.py for common functions between functional and delay tests. Updating functional test.

2026-08-29 09:30:38 +02:00 · 2018-10-04 09:29:44 -07:00
parent bea6b0b5dc
commit 34d8a19871
9 changed files with 435 additions and 193 deletions
@@ -53,6 +53,7 @@ class design(hierarchy_design):
        self.total_write = OPTS.num_rw_ports + OPTS.num_w_ports
        self.total_read = OPTS.num_rw_ports + OPTS.num_r_ports
        self.total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
+        self.num_rw_ports = OPTS.num_rw_ports
        
        # Port indices used for data, address, and control signals
        # Port IDs used to identify port type