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Connect wl_en in all ports to bank.

This commit is contained in:
Matt Guthaus 2019-08-10 12:30:23 -07:00
parent bac684a82a
commit 34d28a19e6
1 changed files with 2 additions and 3 deletions
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5
compiler/modules/bank.py
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@ -915,9 +915,8 @@ class bank(design.design):
connection = [] connection = []
connection.append((self.prefix+"p_en_bar{}".format(port), self.port_data_inst[port].get_pin("p_en_bar").lc())) connection.append((self.prefix+"p_en_bar{}".format(port), self.port_data_inst[port].get_pin("p_en_bar").lc()))
if port in self.read_ports: rbl_wl_name = self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port])
rbl_wl_name = self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port]) connection.append((self.prefix+"wl_en{}".format(port), self.bitcell_array_inst.get_pin(rbl_wl_name).lc()))
connection.append((self.prefix+"wl_en{}".format(port), self.bitcell_array_inst.get_pin(rbl_wl_name).lc()))
if port in self.write_ports: if port in self.write_ports:
connection.append((self.prefix+"w_en{}".format(port), self.port_data_inst[port].get_pin("w_en").lc())) connection.append((self.prefix+"w_en{}".format(port), self.port_data_inst[port].get_pin("w_en").lc()))