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A port option for correct mirroring in port_data.

This commit is contained in:
mrg 2020-06-02 16:50:07 -07:00
parent fce8e878b9
commit 34209dac3d
7 changed files with 9 additions and 11 deletions
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2
compiler/modules/hierarchical_predecode.py
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@ -40,7 +40,6 @@ class hierarchical_predecode(design.design):
def add_modules(self): def add_modules(self):
""" Add the INV and AND gate modules """ """ Add the INV and AND gate modules """
# FIXME: Default parms are required for hard cells for now.
if self.number_of_inputs == 2: if self.number_of_inputs == 2:
self.and_mod = factory.create(module_type="and2_dec", self.and_mod = factory.create(module_type="and2_dec",
height=self.cell_height) height=self.cell_height)
@ -60,7 +59,6 @@ class hierarchical_predecode(design.design):
size=1) size=1)
self.add_mod(self.inv) self.add_mod(self.inv)
def create_layout(self): def create_layout(self):
""" The general organization is from left to right: """ The general organization is from left to right:
1) a set of M2 rails for input signals 1) a set of M2 rails for input signals

1
compiler/modules/port_data.py
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@ -196,6 +196,7 @@ class port_data(design.design):
if self.col_addr_size > 0: if self.col_addr_size > 0:
self.column_mux_array = factory.create(module_type="column_mux_array", self.column_mux_array = factory.create(module_type="column_mux_array",
columns=self.num_cols, columns=self.num_cols,
port=self.port,
word_size=self.word_size, word_size=self.word_size,
bitcell_bl=self.bl_names[self.port], bitcell_bl=self.bl_names[self.port],
bitcell_br=self.br_names[self.port]) bitcell_br=self.br_names[self.port])

1
compiler/modules/precharge_array.py
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@ -7,7 +7,6 @@
# #
import design import design
import debug import debug
from tech import drc
from vector import vector from vector import vector
from sram_factory import factory from sram_factory import factory
from globals import OPTS from globals import OPTS

8
compiler/tests/07_single_level_column_mux_array_pbitcell_test.py
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@ -29,19 +29,19 @@ class single_level_column_mux_pbitcell_test(openram_test):
factory.reset() factory.reset()
debug.info(1, "Testing sample for 2-way column_mux_array in multi-port") debug.info(1, "Testing sample for 2-way column_mux_array in multi-port")
a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") a = factory.create(module_type="single_level_column_mux_array", columns=16, port=0, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a) self.local_check(a)
debug.info(1, "Testing sample for 4-way column_mux_array in multi-port") debug.info(1, "Testing sample for 4-way column_mux_array in multi-port")
a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") a = factory.create(module_type="single_level_column_mux_array", columns=16, port=0, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a) self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (innermost connections)") debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (innermost connections)")
a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") a = factory.create(module_type="single_level_column_mux_array", columns=32, port=0, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a) self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (outermost connections)") debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (outermost connections)")
a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2") a = factory.create(module_type="single_level_column_mux_array", columns=32, port=3, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
self.local_check(a) self.local_check(a)
globals.end_openram() globals.end_openram()

2
compiler/tests/08_precharge_array_1rw1r_test.py
View File

@ -29,7 +29,7 @@ class precharge_test(openram_test):
factory.reset() factory.reset()
debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell") debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell")
pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0") pc = factory.create(module_type="precharge_array", columns=3, port=0, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(pc) self.local_check(pc)
# debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)") # debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)")

2
compiler/tests/08_precharge_array_test.py
View File

@ -23,7 +23,7 @@ class precharge_test(openram_test):
# check precharge array in single port # check precharge array in single port
debug.info(2, "Checking 3 column precharge") debug.info(2, "Checking 3 column precharge")
pc = factory.create(module_type="precharge_array", columns=3) pc = factory.create(module_type="precharge_array", columns=3, port=0)
self.local_check(pc) self.local_check(pc)
globals.end_openram() globals.end_openram()