A port option for correct mirroring in port_data.

2026-09-02 11:08:01 +02:00 · 2020-06-02 16:50:07 -07:00
parent fce8e878b9
commit 34209dac3d
7 changed files with 9 additions and 11 deletions
@@ -23,7 +23,7 @@ class precharge_test(openram_test):

        # check precharge array in single port
        debug.info(2, "Checking 3 column precharge")
-        pc = factory.create(module_type="precharge_array", columns=3)
+        pc = factory.create(module_type="precharge_array", columns=3, port=0)
        self.local_check(pc)

        globals.end_openram()