A port option for correct mirroring in port_data.

compiler/modules/hierarchical_predecode.py

@@ -40,7 +40,6 @@ class hierarchical_predecode(design.design):
     def add_modules(self):
         """ Add the INV and AND gate modules """
 
-        # FIXME: Default parms are required for hard cells for now.
         if self.number_of_inputs == 2:
             self.and_mod = factory.create(module_type="and2_dec",
                                           height=self.cell_height)
@@ -60,7 +59,6 @@ class hierarchical_predecode(design.design):
                                   size=1)
         self.add_mod(self.inv)
 
-
     def create_layout(self):
         """ The general organization is from left to right:
         1) a set of M2 rails for input signals

compiler/modules/port_data.py

@@ -196,6 +196,7 @@ class port_data(design.design):
         if self.col_addr_size > 0:
             self.column_mux_array = factory.create(module_type="column_mux_array",
                                                    columns=self.num_cols,
+                                                   port=self.port,
                                                    word_size=self.word_size,
                                                    bitcell_bl=self.bl_names[self.port],
                                                    bitcell_br=self.br_names[self.port])

compiler/modules/precharge_array.py

@@ -7,7 +7,6 @@
 #
 import design
 import debug
-from tech import drc
 from vector import vector
 from sram_factory import factory
 from globals import OPTS
@@ -26,7 +25,7 @@ class precharge_array(design.design):
         
         self.columns = columns
         self.size = size
-        self.port = port 
+        self.port = port
         self.bitcell_bl = bitcell_bl
         self.bitcell_br = bitcell_br