luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity

Moved manual delay chain declarations from tech files to options.

Browse Source
This commit is contained in:
Hunter Nichols
2019-06-25 15:45:02 -07:00
parent 04ce3d5f45
commit 33c17ac41c
8 changed files with 13 additions and 263 deletions
Download Patch File Download Diff File Expand all files Collapse all files
technology/freepdk45/tech/tech.py
-4
View File
@@ -354,9 +354,6 @@ spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input no
#Parameters related to sense amp enable timing and delay chain/RBL sizing
parameter['le_tau'] = 2.25 #In pico-seconds.
parameter['cap_relative_per_ff'] = 7.5 #Units of Relative Capacitance/ Femto-Farad
parameter["static_delay_stages"] = 4
parameter["static_fanout_per_stage"] = 3
parameter["static_fanout_list"] = parameter["static_delay_stages"]*[parameter["static_fanout_per_stage"]]
parameter["dff_clk_cin"] = 30.6 #relative capacitance
parameter["6tcell_wl_cin"] = 3 #relative capacitance
parameter["min_inv_para_delay"] = 2.4 #Tau delay units
@@ -364,7 +361,6 @@ parameter["sa_en_pmos_size"] = .72 #micro-meters
parameter["sa_en_nmos_size"] = .27 #micro-meters
parameter["sa_inv_pmos_size"] = .54 #micro-meters
parameter["sa_inv_nmos_size"] = .27 #micro-meters
parameter["rbl_height_percentage"] = .5 #Height of RBL compared to bitcell array
parameter['bitcell_drain_cap'] = 0.1 #In Femto-Farad, approximation of drain capacitance
###################################################
technology/scn4m_subm/tech/tech.py
-4
View File
@@ -321,16 +321,12 @@ spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input no
parameter['le_tau'] = 23 #In pico-seconds.
parameter["min_inv_para_delay"] = .73 #In relative delay units
parameter['cap_relative_per_ff'] = .91 #Units of Relative Capacitance/ Femto-Farad
parameter["static_delay_stages"] = 4
parameter["static_fanout_per_stage"] = 3
parameter["static_fanout_list"] = parameter["static_delay_stages"]*[parameter["static_fanout_per_stage"]]
parameter["dff_clk_cin"] = 27.5 #In relative capacitance units
parameter["6tcell_wl_cin"] = 2 #In relative capacitance units
parameter["sa_en_pmos_size"] = 24*_lambda_
parameter["sa_en_nmos_size"] = 9*_lambda_
parameter["sa_inv_pmos_size"] = 18*_lambda_
parameter["sa_inv_nmos_size"] = 9*_lambda_
parameter["rbl_height_percentage"] = .5 #Height of RBL compared to bitcell array
parameter['bitcell_drain_cap'] = 0.2 #In Femto-Farad, approximation of drain capacitance
###################################################