Moved manual delay chain declarations from tech files to options.

compiler/modules/bitcell_array.py

@@ -154,7 +154,7 @@ class bitcell_array(design.design):
         # Dynamic Power from Bitline
         bl_wire = self.gen_bl_wire()
         cell_load = 2 * bl_wire.return_input_cap() 
-        bl_swing = parameter["rbl_height_percentage"]
+        bl_swing = OPTS.rbl_delay_percentage
         freq = spice["default_event_rate"]
         bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
         

compiler/modules/control_logic.py

@@ -143,10 +143,10 @@ class control_logic(design.design):
             self.delay_chain_resized = False
             c = reload(__import__(OPTS.replica_bitline))
             replica_bitline = getattr(c, OPTS.replica_bitline)
-            bitcell_loads = int(math.ceil(self.num_rows * parameter["rbl_height_percentage"]))
+            bitcell_loads = int(math.ceil(self.num_rows * OPTS.rbl_delay_percentage))
             #Use a model to determine the delays with that heuristic
             if OPTS.use_tech_delay_chain_size: #Use tech parameters if set.
-                fanout_list = parameter["static_fanout_list"]
+                fanout_list = OPTS.delay_chain_stages*[OPTS.delay_chain_fanout_per_stage]
                 debug.info(1, "Using tech parameters to size delay chain: fanout_list={}".format(fanout_list))
                 self.replica_bitline = factory.create(module_type="replica_bitline",
                                                       delay_fanout_list=fanout_list,

compiler/modules/replica_bitline.py

@@ -25,6 +25,8 @@ class replica_bitline(design.design):
 
         self.bitcell_loads = bitcell_loads
         self.delay_fanout_list = delay_fanout_list
+        if len(delay_fanout_list) == 0 or len(delay_fanout_list)%2 == 1:
+            debug.error('Delay chain must contain an even amount of stages to maintain polarity.',1)
 
         self.create_netlist()
         if not OPTS.netlist_only: