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fixing drc on rom bank, mostly spacing tweaks

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SWalker
2023-10-31 23:24:21 -07:00
parent 75f7a5847f
commit 3271c5e73c
4 changed files with 9 additions and 5 deletions
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compiler/modules/pinv_dec.py
+5 -1
View File
@@ -187,7 +187,11 @@ class pinv_dec(pinv):
# Pick point at right most of NMOS and connect over to PMOS
nmos_drain_pos = nmos_drain_pin.lc()
right_side = vector(self.width, nmos_drain_pos.y)
if self.flip_io:
right_side = vector(self.pmos_inst.get_pin("D").cx(), nmos_drain_pos.y)
else:
right_side = vector(self.width, nmos_drain_pos.y)
self.add_layout_pin_segment_center("Z",
self.route_layer,
compiler/modules/rom_bank.py
+1 -1
View File
@@ -297,7 +297,7 @@ class rom_bank(design,rom_verilog):
def place_bitline_inverter(self):
self.bitline_inv_inst.place(offset=[0,0], rotate=90)
inv_y_offset = self.array_inst.by() - self.bitline_inv_inst.width - 2 * self.m1_pitch
inv_y_offset = self.array_inst.by() - self.bitline_inv_inst.width - 1.5 * self.m1_pitch
inv_x_offset = self.array_inst.get_pin("bl_0_0").cx() - self.bitline_inv_inst.get_pin("out_0").cx()
self.inv_offset = vector(inv_x_offset, inv_y_offset)
compiler/modules/rom_base_array.py
+2 -2
View File
@@ -234,12 +234,12 @@ class rom_base_array(bitcell_base_array):
bottom = vector(pin.cx(), pin.by())
top = vector(pin.cx(), gnd_y)
self.add_via_stack_center(offset=top, from_layer=self.bitline_layer, to_layer=self.supply_stack[0])
self.add_via_center(offset=bottom, layers=self.supply_stack)
# self.add_via_center(offset=bottom, layers=self.supply_stack)
self.add_layout_pin_rect_ends(name="gnd", layer=self.supply_stack[0], start=bottom, end=top)
self.remove_layout_pin("gnd_tmp")
self.add_segment_center(layer=self.supply_stack[2], start=vector(min_x, bottom.y), end=vector(max_x, bottom.y))
# self.add_segment_center(layer=self.supply_stack[2], start=vector(min_x, bottom.y), end=vector(max_x, bottom.y))
self.add_segment_center(layer=self.bitline_layer, start=gnd_l, end=vector(min_x, gnd_l.y))
self.add_segment_center(layer=self.bitline_layer, start=gnd_r, end=vector(max_x, gnd_r.y))