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Remove sense enable during writes

This commit is contained in:
Matt Guthaus 2019-09-07 20:04:48 -07:00
parent e5db02f7d8
commit 322af0ec09
1 changed files with 32 additions and 23 deletions
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23
compiler/modules/control_logic.py
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@ -236,8 +236,9 @@ class control_logic(design.design):
def does_sen_total_timing_match(self):
"""Compare the total delays of the sense amp enable and wordline"""
self.set_sen_wl_delays()
#The sen delay must always be bigger than than the wl delay. This decides how much larger the sen delay must be before
#a re-size is warranted.
# The sen delay must always be bigger than than the wl
# delay. This decides how much larger the sen delay must be
# before a re-size is warranted.
if self.wl_delay*self.wl_timing_tolerance >= self.sen_delay:
return False
else:
@ -343,7 +344,7 @@ class control_logic(design.design):
# list of output control signals (for making a vertical bus)
if self.port_type == "rw":
self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "we", "clk_buf", "cs_bar", "cs"]
self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "we", "clk_buf", "we_bar", "cs"]
elif self.port_type == "r":
self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"]
else:
@ -639,11 +640,14 @@ class control_logic(design.design):
def create_sen_row(self):
""" Create the sense enable buffer. """
if self.port_type=="rw":
input_name = "we_bar"
else:
input_name = "cs_bar"
# GATE FOR S_EN
# Uses cs_bar (not we_bar) for feed-thru reads
self.s_en_gate_inst = self.add_inst(name="buf_s_en_and",
mod=self.sen_and3)
self.connect_inst(["rbl_bl_delay", "gated_clk_bar", "cs_bar", "s_en", "vdd", "gnd"])
self.connect_inst(["rbl_bl_delay", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"])
def place_sen_row(self,row):
@ -656,7 +660,12 @@ class control_logic(design.design):
def route_sen(self):
sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", "cs_bar"])
if self.port_type=="rw":
input_name = "we_bar"
else:
input_name = "cs_bar"
sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name])
self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.rail_offsets)
self.connect_output(self.s_en_gate_inst, "Z", "s_en")
@ -733,7 +742,7 @@ class control_logic(design.design):
def route_dffs(self):
if self.port_type == "rw":
dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_0"], ["cs", "we", "cs_bar"])
dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"])
elif self.port_type == "r":
dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"])
else: