mirror of https://github.com/VLSIDA/OpenRAM.git
Change LWL layers
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@ -239,7 +239,12 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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out_loc = out_pin.lc()
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mid_loc = vector(self.wl_insts[port].lx() - 1.5 * self.m3_pitch, out_loc.y)
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in_loc = in_pin.rc()
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self.add_path(out_pin.layer, [out_loc, mid_loc, in_loc])
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self.add_path(out_pin.layer, [out_loc, mid_loc])
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self.add_via_stack_center(from_layer=out_pin.layer,
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to_layer=in_pin.layer,
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offset=mid_loc)
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self.add_path(in_pin.layer, [mid_loc, in_loc])
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def get_main_array_top(self):
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return self.bitcell_array_inst.by() + self.bitcell_array.get_main_array_top()
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