mirror of https://github.com/VLSIDA/OpenRAM.git
Fix precharge nwell contact spacing DRC violatin.
This commit is contained in:
parent
e46a4fb115
commit
31c192c2e9
|
|
@ -128,7 +128,7 @@ class precharge(pgate.pgate):
|
||||||
"""Adds a nwell tap to connect to the vdd rail"""
|
"""Adds a nwell tap to connect to the vdd rail"""
|
||||||
# adds the contact from active to metal1
|
# adds the contact from active to metal1
|
||||||
well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1,0) \
|
well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1,0) \
|
||||||
+ vector(0, self.upper_pmos1_pos.y + self.pmos.height + drc["well_extend_active"])
|
+ vector(0, self.upper_pmos1_inst.uy() + contact.well.height/2 + drc["well_extend_active"])
|
||||||
self.add_contact_center(layers=("active", "contact", "metal1"),
|
self.add_contact_center(layers=("active", "contact", "metal1"),
|
||||||
offset=well_contact_pos,
|
offset=well_contact_pos,
|
||||||
implant_type="n",
|
implant_type="n",
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue