Replaced instances of addr_size with bank_addr

compiler/modules/bank.py

@@ -93,7 +93,7 @@ class bank(design):
             for bit in range(self.word_size + self.num_spare_cols):
                 self.add_pin("din{0}_{1}".format(port, bit), "INPUT")
         for port in self.all_ports:
-            for bit in range(self.addr_size):
+            for bit in range(self.bank_addr_size):
                 self.add_pin("addr{0}_{1}".format(port, bit), "INPUT")
 
         # For more than one bank, we have a bank select and name
@@ -326,11 +326,11 @@ class bank(design):
         
         self.row_addr_size = ceil(log(self.num_rows, 2))
         self.col_addr_size = int(log(self.words_per_row, 2))
-        self.addr_size = self.col_addr_size + self.row_addr_size
+        self.bank_addr_size = self.col_addr_size + self.row_addr_size
 
         debug.check(self.num_rows_temp * self.num_cols * self.num_banks ==self.word_size * self.num_words,
                     "Invalid bank sizes.")
-        debug.check(self.addr_size==self.col_addr_size + self.row_addr_size,
+        debug.check(self.bank_addr_size==self.col_addr_size + self.row_addr_size,
                     "Invalid address break down.")
 
         # The order of the control signals on the control bus:

compiler/modules/sram_1bank.py

@@ -57,7 +57,7 @@ class sram_1bank(design, verilog, lef):
             for bit in range(self.word_size + self.num_spare_cols):
                 self.add_pin("din{0}[{1}]".format(port, bit), "INPUT")
         for port in self.all_ports:
-            for bit in range(self.addr_size):
+            for bit in range(self.bank_addr_size):
                 self.add_pin("addr{0}[{1}]".format(port, bit), "INPUT")
 
         # These are used to create the physical pins
@@ -377,7 +377,7 @@ class sram_1bank(design, verilog, lef):
         """ Compute the independent bus widths shared between two and four bank SRAMs """
 
         # address size + control signals + one-hot bank select signals
-        self.num_vertical_line = self.addr_size + self.control_size + 1# + log(self.num_banks, 2) + 1
+        self.num_vertical_line = self.bank_addr_size + self.control_size + 1# + log(self.num_banks, 2) + 1
         # data bus size
         self.num_horizontal_line = self.word_size
 
@@ -419,7 +419,7 @@ class sram_1bank(design, verilog, lef):
                                                                        names=self.control_bus_names[port],
                                                                        length=self.vertical_bus_height)
 
-            self.addr_bus_names=["A{0}[{1}]".format(port, i) for i in range(self.addr_size)]
+            self.addr_bus_names=["A{0}[{1}]".format(port, i) for i in range(self.bank_addr_size)]
             self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2",
                                                                                 pitch=self.m2_pitch,
                                                                                 offset=self.addr_bus_offset,

compiler/modules/sram_base.py

@@ -50,7 +50,7 @@ class sram_base(design, verilog, lef):
                 self.add_pin("din{0}[{1}]".format(port, bit), "INPUT")
 
         for port in self.all_ports:
-            for bit in range(self.addr_size):
+            for bit in range(self.bank_addr_size):
                 self.add_pin("addr{0}[{1}]".format(port, bit), "INPUT")
 
         # These are used to create the physical pins
@@ -374,7 +374,7 @@ class sram_base(design, verilog, lef):
         """ Compute the independent bus widths shared between two and four bank SRAMs """
 
         # address size + control signals + one-hot bank select signals
-        self.num_vertical_line = self.addr_size + self.control_size + log(self.num_banks, 2) + 1
+        self.num_vertical_line = self.bank_addr_size + self.control_size + log(self.num_banks, 2) + 1
         # data bus size
         self.num_horizontal_line = self.word_size
 
@@ -416,7 +416,7 @@ class sram_base(design, verilog, lef):
                                                                        names=self.control_bus_names[port],
                                                                        length=self.vertical_bus_height)
 
-            self.addr_bus_names=["A{0}[{1}]".format(port, i) for i in range(self.addr_size)]
+            self.addr_bus_names=["A{0}[{1}]".format(port, i) for i in range(self.bank_addr_size)]
             self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2",
                                                                                 pitch=self.m2_pitch,
                                                                                 offset=self.addr_bus_offset,

compiler/modules/sram_config.py

@@ -121,8 +121,7 @@ class sram_config:
         self.row_addr_size = ceil(log(self.num_rows, 2))
         self.col_addr_size = int(log(self.words_per_row, 2))
         self.bank_addr_size = self.col_addr_size + self.row_addr_size
-        #self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
-        self.addr_size = self.bank_addr_size
+        self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
         debug.info(1, "Row addr size: {}".format(self.row_addr_size)
                    + " Col addr size: {}".format(self.col_addr_size)
                    + " Bank addr size: {}".format(self.bank_addr_size))

compiler/modules/sram_multibank.py

@@ -21,7 +21,7 @@ class sram_multibank:
             'w_ports': w_ports,
             'banks': list(range(sram.num_banks)),
             'data_width': sram.word_size,
-            'addr_width': sram.addr_size + ceil(log(sram.num_banks, 2)),
+            'addr_width': sram.bank_addr_size + ceil(log(sram.num_banks, 2)),
             'bank_sel': ceil(log(sram.num_banks, 2)),
             'num_wmask': sram.num_wmasks
             }