Update README to include DRC/LVS tool in example

2026-09-02 02:57:53 +02:00 · 2019-01-03 15:37:53 -08:00
parent 4a5c18b6cc
commit 30c74accaf
1 changed files with 6 additions and 0 deletions
@@ -98,6 +98,12 @@ output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)

 # Disable analytical models for full characterization (WARNING: slow!)
 # analytical_delay = False
+
+# To force this to use magic and netgen for DRC/LVS/PEX
+# Could be calibre for FreePDK45
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"
 ```

 You can then run OpenRAM by executing: