Change inheritance inits to use super

compiler/modules/bank.py

@@ -36,7 +36,7 @@ class bank(design.design):
                 
         if name == "":
             name = "bank_{0}_{1}".format(self.word_size, self.num_words)
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(2, "create sram of size {0} with {1} words".format(self.word_size,
                                                                       self.num_words))
         

compiler/modules/bank_select.py

@@ -24,7 +24,7 @@ class bank_select(design.design):
     """
 
     def __init__(self, name="bank_select", port="rw"):
-        design.design.__init__(self, name)
+        super().__init__(name)
 
         self.port = port
         

compiler/modules/control_logic.py

@@ -23,7 +23,7 @@ class control_logic(design.design):
     def __init__(self, num_rows, words_per_row, word_size, spare_columns=None, sram=None, port_type="rw", name=""):
         """ Constructor """
         name = "control_logic_" + port_type
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {}".format(name))
         self.add_comment("num_rows: {0}".format(num_rows))
         self.add_comment("words_per_row: {0}".format(words_per_row))

compiler/modules/delay_chain.py

@@ -21,7 +21,7 @@ class delay_chain(design.design):
 
     def __init__(self, name, fanout_list):
         """init function"""
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "creating delay chain {0}".format(str(fanout_list)))
         self.add_comment("fanouts: {0}".format(str(fanout_list)))
         

compiler/modules/dff_array.py

@@ -24,7 +24,7 @@ class dff_array(design.design):
 
         if name=="":
             name = "dff_array_{0}x{1}".format(rows, columns)
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0} rows={1} cols={2}".format(self.name, self.rows, self.columns))
         self.add_comment("rows: {0} cols: {1}".format(rows, columns))
         

compiler/modules/dff_buf.py

@@ -27,7 +27,7 @@ class dff_buf(design.design):
         if name=="":
             name = "dff_buf_{0}".format(dff_buf.unique_id)
             dff_buf.unique_id += 1
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {}".format(self.name))
         self.add_comment("inv1: {0} inv2: {1}".format(inv1_size, inv2_size))
         

compiler/modules/dff_buf_array.py

@@ -27,7 +27,7 @@ class dff_buf_array(design.design):
         if name=="":
             name = "dff_buf_array_{0}x{1}_{2}".format(rows, columns, dff_buf_array.unique_id)
             dff_buf_array.unique_id += 1
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {}".format(self.name))
         self.add_comment("rows: {0} cols: {1}".format(rows, columns))
         self.add_comment("inv1: {0} inv2: {1}".format(inv1_size, inv2_size))

compiler/modules/dff_inv.py

@@ -25,7 +25,7 @@ class dff_inv(design.design):
         if name=="":
             name = "dff_inv_{0}".format(dff_inv.unique_id)
             dff_inv.unique_id += 1
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {}".format(self.name))
         self.add_comment("inv: {0}".format(inv_size))
 

compiler/modules/dff_inv_array.py

@@ -27,7 +27,7 @@ class dff_inv_array(design.design):
         if name=="":
             name = "dff_inv_array_{0}x{1}_{2}".format(rows, columns, dff_inv_array.unique_id)
             dff_inv_array.unique_id += 1
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {}".format(self.name))
         self.add_comment("rows: {0} cols: {1}".format(rows, columns))
         self.add_comment("inv1: {0}".format(inv1_size))

compiler/modules/hierarchical_decoder.py

@@ -18,7 +18,7 @@ class hierarchical_decoder(design.design):
     Dynamically generated hierarchical decoder.
     """
     def __init__(self, name, num_outputs):
-        design.design.__init__(self, name)
+        super().__init__(name)
 
         self.AND_FORMAT = "DEC_AND_{0}"
         

compiler/modules/hierarchical_predecode.py

@@ -31,7 +31,7 @@ class hierarchical_predecode(design.design):
         self.column_decoder = (height != b.height)
             
         self.number_of_outputs = int(math.pow(2, self.number_of_inputs))
-        design.design.__init__(self, name)
+        super().__init__(name)
     
     def add_pins(self):
         for k in range(self.number_of_inputs):

compiler/modules/hierarchical_predecode2x4.py

@@ -14,7 +14,7 @@ class hierarchical_predecode2x4(hierarchical_predecode):
     Pre 2x4 decoder used in hierarchical_decoder.
     """
     def __init__(self, name, height=None):
-        hierarchical_predecode.__init__(self, name, 2, height)
+        super().__init__( name, 2, height)
 
         self.create_netlist()
         if not OPTS.netlist_only:

compiler/modules/hierarchical_predecode3x8.py

@@ -14,7 +14,7 @@ class hierarchical_predecode3x8(hierarchical_predecode):
     Pre 3x8 decoder used in hierarchical_decoder.
     """
     def __init__(self, name, height=None):
-        hierarchical_predecode.__init__(self, name, 3, height)
+        super().__init__(name, 3, height)
 
         self.create_netlist()
         if not OPTS.netlist_only:

compiler/modules/hierarchical_predecode4x16.py

@@ -14,7 +14,7 @@ class hierarchical_predecode4x16(hierarchical_predecode):
     Pre 4x16 decoder used in hierarchical_decoder.
     """
     def __init__(self, name, height=None):
-        hierarchical_predecode.__init__(self, name, 4, height)
+        super().__init__(name, 4, height)
 
         self.create_netlist()
         if not OPTS.netlist_only:

compiler/modules/multibank.py

@@ -26,7 +26,7 @@ class multibank(design.design):
 
     def __init__(self, name, word_size, num_words, words_per_row, num_banks=1):
 
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(2, "create sram of size {0} with {1} words".format(word_size,num_words))
 
         self.word_size = word_size

compiler/modules/port_address.py

@@ -25,7 +25,7 @@ class port_address(design.design):
         
         if name == "":
             name = "port_address_{0}_{1}".format(cols, rows)
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(2, "create data port of cols {0} rows {1}".format(cols, rows))
 
         self.create_netlist()

compiler/modules/port_data.py

@@ -32,7 +32,7 @@ class port_data(design.design):
 
         if name == "":
             name = "port_data_{0}".format(self.port)
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(2,
                    "create data port of size {0} with {1} words per row".format(self.word_size,
                                                                                    self.words_per_row))

compiler/modules/precharge_array.py

@@ -20,7 +20,7 @@ class precharge_array(design.design):
     """
 
     def __init__(self, name, columns, size=1, bitcell_bl="bl", bitcell_br="br", column_offset=0):
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
         self.add_comment("cols: {0} size: {1} bl: {2} br: {3}".format(columns, size, bitcell_bl, bitcell_br))
         

compiler/modules/replica_column.py

@@ -22,7 +22,7 @@ class replica_column(design.design):
 
     def __init__(self, name, rows, left_rbl, right_rbl, replica_bit,
                  column_offset=0):
-        design.design.__init__(self, name)
+        super().__init__(name)
 
         self.rows = rows
         self.left_rbl = left_rbl

compiler/modules/sense_amp.py

@@ -50,7 +50,7 @@ class sense_amp(design.design):
         return props.sense_amp.pin.en
 
     def __init__(self, name):
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(2, "Create sense_amp")
 
         self.width = sense_amp.width

compiler/modules/sense_amp_array.py

@@ -22,7 +22,7 @@ class sense_amp_array(design.design):
 
     def __init__(self, name, word_size, words_per_row, num_spare_cols=None, column_offset=0):
 
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
         self.add_comment("word_size {0}".format(word_size))
         self.add_comment("words_per_row: {0}".format(words_per_row))

compiler/modules/single_level_column_mux_array.py

@@ -21,7 +21,7 @@ class single_level_column_mux_array(design.design):
     """
 
     def __init__(self, name, columns, word_size, bitcell_bl="bl", bitcell_br="br", column_offset=0):
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
         self.add_comment("cols: {0} word_size: {1} bl: {2} br: {3}".format(columns, word_size, bitcell_bl, bitcell_br))
 

compiler/modules/tri_gate_array.py

@@ -19,7 +19,7 @@ class tri_gate_array(design.design):
 
     def __init__(self, columns, word_size, name):
         """Intial function of tri gate array """
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
 
         self.columns = columns

compiler/modules/wordline_driver_array.py

@@ -19,7 +19,7 @@ class wordline_driver_array(design.design):
     """
 
     def __init__(self, name, rows, cols):
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
         self.add_comment("rows: {0} cols: {1}".format(rows, cols))
         

compiler/modules/write_driver_array.py

@@ -21,7 +21,7 @@ class write_driver_array(design.design):
 
     def __init__(self, name, columns, word_size, num_spare_cols=None, write_size=None, column_offset=0):
 
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
         self.add_comment("columns: {0}".format(columns))
         self.add_comment("word_size {0}".format(word_size))

compiler/modules/write_mask_and_array.py

@@ -19,7 +19,7 @@ class write_mask_and_array(design.design):
     """
 
     def __init__(self, name, columns, word_size, write_size, column_offset=0):
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
         self.add_comment("columns: {0}".format(columns))
         self.add_comment("word_size {0}".format(word_size))