Small format cleanup

compiler/bitcells/pbitcell.py

@@ -7,7 +7,7 @@
 #
 import contact
 import debug
-from tech import drc, parameter
+from tech import drc, parameter, layer
 from vector import vector
 from ptx import ptx
 from globals import OPTS
@@ -975,6 +975,7 @@ class pbitcell(bitcell_base.bitcell_base):
         """
         Connects wells between ptx modules and places well contacts
         """
+        if "pwell" in layer:
             # extend pwell to encompass entire nmos region of the cell up to the
             # height of the tallest nmos transistor
             max_nmos_well_height = max(self.inverter_nmos.well_height,
@@ -993,6 +994,7 @@ class pbitcell(bitcell_base.bitcell_base):
             
         # extend nwell to encompass inverter_pmos
         # calculate offset of the left pmos well
+        if "nwell" in layer:
             inverter_well_xpos = -(self.inverter_nmos.active_width + 0.5 * self.inverter_to_inverter_spacing) \
                                  - self.nwell_enclose_active
             inverter_well_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height \

compiler/pgates/ptx.py

@@ -196,6 +196,8 @@ class ptx(design.design):
             # The well is not included in the height and width
             self.height = self.poly_height
             self.width = self.active_width
+            self.well_height = self.height
+            self.well_width = self.width
 
         # This is the center of the first active contact offset (centered vertically)
         self.contact_offset = self.active_offset + vector(0.5 * self.active_contact.width,