PEP8 cleanup

2020-11-17 16:56:00 -08:00 · 2020-11-17 16:56:00 -08:00 · 305b546ad5
parent 02c1fac3b8
commit 305b546ad5
1 changed files with 7 additions and 9 deletions
--- a/compiler/base/verilog.py
+++ b/compiler/base/verilog.py
@ -84,7 +84,6 @@ class verilog:
        self.vf.write("endmodule\n")
        self.vf.close()

-
    def register_inputs(self, port):
        """
        Register the control signal, address and data inputs.
@ -151,7 +150,6 @@ class verilog:

        self.vf.write("  end\n\n")

-
    def add_inputs_outputs(self, port):
        """
        Add the module input and output declaration for a port.