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PEP8 Cleanup and reverse pitch offset of col addr routing

This commit is contained in:
mrg 2020-02-06 22:59:30 +00:00
parent 4b06ab9eaf
commit 2ff058f5d5
2 changed files with 17 additions and 19 deletions
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34
compiler/modules/bank.py
View File

@ -5,19 +5,15 @@
# (acting for and on behalf of Oklahoma State University) # (acting for and on behalf of Oklahoma State University)
# All rights reserved. # All rights reserved.
# #
import sys
from tech import drc, parameter
import debug import debug
import design import design
import math
from math import log,sqrt,ceil
import contact
import pgates
from sram_factory import factory from sram_factory import factory
from math import log
from tech import drc
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
class bank(design.design): class bank(design.design):
""" """
Dynamically generated a single bank including bitcell array, Dynamically generated a single bank including bitcell array,
@ -499,6 +495,8 @@ class bank(design.design):
Create a 2:4 or 3:8 column address decoder. Create a 2:4 or 3:8 column address decoder.
""" """
# Height is a multiple of DFF so that it can be staggered
# and rows do not align with the control logic module
self.dff = factory.create(module_type="dff") self.dff = factory.create(module_type="dff")
if self.col_addr_size == 0: if self.col_addr_size == 0:
@ -867,7 +865,6 @@ class bank(design.design):
route_map = list(zip(decode_pins, column_mux_pins)) route_map = list(zip(decode_pins, column_mux_pins))
self.create_vertical_channel_route(route_map, offset, self.m1_stack) self.create_vertical_channel_route(route_map, offset, self.m1_stack)
def add_lvs_correspondence_points(self): def add_lvs_correspondence_points(self):
""" This adds some points for easier debugging if LVS goes wrong. """ This adds some points for easier debugging if LVS goes wrong.
These should probably be turned off by default though, since extraction These should probably be turned off by default though, since extraction
@ -912,7 +909,6 @@ class bank(design.design):
layer="m1", layer="m1",
offset=data_pin.center()) offset=data_pin.center())
def route_control_lines(self, port): def route_control_lines(self, port):
""" Route the control lines of the entire bank """ """ Route the control lines of the entire bank """
@ -920,23 +916,25 @@ class bank(design.design):
# From control signal to the module pin # From control signal to the module pin
# Connection from the central bus to the main control block crosses # Connection from the central bus to the main control block crosses
# pre-decoder and this connection is in metal3 # pre-decoder and this connection is in metal3
write_inst = 0
read_inst = 0
connection = [] connection = []
connection.append((self.prefix+"p_en_bar{}".format(port), self.port_data_inst[port].get_pin("p_en_bar").lc())) connection.append((self.prefix + "p_en_bar{}".format(port),
self.port_data_inst[port].get_pin("p_en_bar").lc()))
rbl_wl_name = self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port]) rbl_wl_name = self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port])
connection.append((self.prefix+"wl_en{}".format(port), self.bitcell_array_inst.get_pin(rbl_wl_name).lc())) connection.append((self.prefix + "wl_en{}".format(port),
self.bitcell_array_inst.get_pin(rbl_wl_name).lc()))
if port in self.write_ports: if port in self.write_ports:
if port % 2: if port % 2:
connection.append((self.prefix+"w_en{}".format(port), self.port_data_inst[port].get_pin("w_en").rc())) connection.append((self.prefix + "w_en{}".format(port),
self.port_data_inst[port].get_pin("w_en").rc()))
else: else:
connection.append((self.prefix+"w_en{}".format(port), self.port_data_inst[port].get_pin("w_en").lc())) connection.append((self.prefix + "w_en{}".format(port),
self.port_data_inst[port].get_pin("w_en").lc()))
if port in self.read_ports: if port in self.read_ports:
connection.append((self.prefix+"s_en{}".format(port), self.port_data_inst[port].get_pin("s_en").lc())) connection.append((self.prefix + "s_en{}".format(port),
self.port_data_inst[port].get_pin("s_en").lc()))
for (control_signal, pin_pos) in connection: for (control_signal, pin_pos) in connection:
control_mid_pos = self.bus_xoffset[port][control_signal] control_mid_pos = self.bus_xoffset[port][control_signal]
@ -960,7 +958,7 @@ class bank(design.design):
self.add_via_center(layers=self.m1_stack, self.add_via_center(layers=self.m1_stack,
offset=control_pos) offset=control_pos)
def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True): def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True):
"""Get the all the stage efforts for each stage in the path within the bank clk_buf to a wordline""" """Get the all the stage efforts for each stage in the path within the bank clk_buf to a wordline"""
#Decoder is assumed to have settled before the negative edge of the clock. Delay model relies on this assumption #Decoder is assumed to have settled before the negative edge of the clock. Delay model relies on this assumption
stage_effort_list = [] stage_effort_list = []

2
compiler/sram/sram_1bank.py
View File

@ -320,7 +320,7 @@ class sram_1bank(sram_base):
""" Connect the output of the col flops to the bank pins """ """ Connect the output of the col flops to the bank pins """
for port in self.all_ports: for port in self.all_ports:
if port%2: if port%2:
offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.word_size+4)*self.m1_pitch) offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.word_size+2)*self.m1_pitch)
else: else:
offset = self.col_addr_dff_insts[port].ul() + vector(0, 2*self.m1_pitch) offset = self.col_addr_dff_insts[port].ul() + vector(0, 2*self.m1_pitch)