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change col mux array poly routing from straight to 'L'

This commit is contained in:
Jesse Cirimelli-Low 2021-11-17 17:22:03 -08:00
parent c8139cf145
commit 2fb08af684
1 changed files with 5 additions and 2 deletions
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7
compiler/modules/column_mux_array.py
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@ -177,13 +177,16 @@ class column_mux_array(design.design):
# height to connect the gate to the correct horizontal row # height to connect the gate to the correct horizontal row
# sel_height = self.get_pin("sel_{}".format(sel_index)).by() # sel_height = self.get_pin("sel_{}".format(sel_index)).by()
# use the y offset from the sel pin and the x offset from the gate # use the y offset from the sel pin and the x offset from the gate
offset = vector(gate_offset.x, offset = vector(gate_offset.x,
self.get_pin("sel_{}".format(sel_index)).cy()) self.get_pin("sel_{}".format(sel_index)).cy())
bl_offset = offset + vector((self.mux_inst[col].get_pin("br_out").bc().x - self.mux_inst[col].get_pin("bl_out").bc().x)/2, 0)
self.add_via_stack_center(from_layer="poly", self.add_via_stack_center(from_layer="poly",
to_layer=self.sel_layer, to_layer=self.sel_layer,
offset=offset, offset=bl_offset,
directions=self.via_directions) directions=self.via_directions)
self.add_path("poly", [offset, gate_offset]) self.add_path("poly", [offset, gate_offset, bl_offset])
def route_bitlines(self): def route_bitlines(self):
""" Connect the output bit-lines to form the appropriate width mux """ """ Connect the output bit-lines to form the appropriate width mux """