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Merge branch 'dev' into delay_ctrl

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This commit is contained in:
Sam Crow
2023-06-05 16:24:48 -07:00
parent f01e73328d 0a4a36488b
commit 2f5d3b6faf
690 changed files with 347277 additions and 7674 deletions
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compiler/tests/00_code_format_check_test.py
+76 -9
View File
@@ -1,18 +1,18 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os, re
import unittest
from testutils import *
import sys, os,re
import globals
import debug
import openram
from openram import debug
class code_format_test(openram_test):
"Run a test to check for tabs instead of spaces in the all source files."
@@ -28,13 +28,15 @@ class code_format_test(openram_test):
continue
errors += check_file_format_tab(code)
errors += check_file_format_carriage(code)
errors += check_file_format_whitespace(code)
# Check for "print"
for code in source_codes:
if re.search("gdsMill", code):
continue
if re.search("debug.py$", code):
continue
if re.search("openram.py$", code):
if re.search("sram_compiler.py$", code):
continue
if re.search("testutils.py$", code):
continue
@@ -42,6 +44,11 @@ class code_format_test(openram_test):
continue
errors += check_print_output(code)
# Check for copyright
for code in source_codes:
if re.search("gdsMill", code):
continue
errors += check_copyright(code)
# fails if there are any tabs in any files
self.assertEqual(errors, 0)
@@ -51,7 +58,7 @@ def setup_files(path):
files = []
for (dir, _, current_files) in os.walk(path):
for f in current_files:
files.append(os.getenv("OPENRAM_HOME"))
files.append(os.path.join(dir, f))
nametest = re.compile("\.py$", re.IGNORECASE)
select_files = list(filter(nametest.search, files))
return select_files
@@ -92,16 +99,43 @@ def check_file_format_carriage(file_name):
if len(key_positions)>10:
line_numbers = key_positions[:10] + [" ..."]
else:
line_numbers = key_positoins
line_numbers = key_positions
debug.info(0, '\nFound ' + str(len(key_positions)) + ' carriage returns in ' +
str(file_name) + ' (lines ' + ",".join(str(x) for x in line_numbers) + ')')
f.close()
return len(key_positions)
def check_file_format_whitespace(file_name):
"""
Check if file contains a line with whitespace at the end
and return the number of these lines.
"""
f = open(file_name, "r")
key_positions = []
for num, line in enumerate(f.readlines()):
if re.match(r".*[ \t]$", line):
key_positions.append(num)
if len(key_positions) > 0:
if len(key_positions) > 10:
line_numbers = key_positions[:10] + [" ..."]
else:
line_numbers = key_positions
debug.info(0, "\nFound " + str(len(key_positions)) + " ending whitespace in " +
str(file_name) + " (lines " + ",".join(str(x) for x in line_numbers) + ")")
f.close()
return len(key_positions)
def check_print_output(file_name):
"""Check if any files (except debug.py) call the _print_ function. We should
use the debug output with verbosity instead!"""
skip_files = ["printGDS.py", "uniquifyGDS.py", "processGDS.py", "model_data_util.py"]
base_file_name = os.path.basename(file_name)
if base_file_name in skip_files:
return(0)
file = open(file_name, "r+b")
line = file.read().decode('utf-8')
# skip comments with a hash
@@ -117,9 +151,42 @@ def check_print_output(file_name):
return(count)
def check_copyright(file_name):
""" Check if any file doesn't contain the copyright at the top. """
from datetime import date
year = date.today().year
old_copyright = ("# See LICENSE for licensing information.\n"
"#\n"
"# Copyright (c) 2016-{} Regents of the University of California and The Board\n"
"# of Regents for the Oklahoma Agricultural and Mechanical College\n"
"# (acting for and on behalf of Oklahoma State University)\n"
"# All rights reserved.\n"
"#\n").format(year)
new_copyright = ("# See LICENSE for licensing information.\n"
"#\n"
"# Copyright (c) 2016-{} Regents of the University of California, Santa Cruz\n"
"# All rights reserved.\n"
"#\n").format(year)
skip_files = []
base_file_name = os.path.basename(file_name)
if base_file_name in skip_files:
return 0
file = open(file_name, "r")
line = file.read()
file.close()
# Skip possible shebang at the top
line = re.sub(r'#!.*\n', '', line)
# Check if copyright is missing
if not line.startswith(old_copyright) and not line.startswith(new_copyright):
debug.info(0, "\nFound missing/wrong copyright in " + file_name)
return 1
return 0
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/01_library_test.py
+12 -11
View File
@@ -1,25 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os, re
import unittest
from testutils import *
import sys, os,re
import globals
from globals import OPTS
import debug
import openram
from openram import debug
from openram import OPTS
class library_lvs_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import verify
openram.init_openram(config_file, is_unit_test=True)
from openram import verify
(gds_dir, sp_dir, allnames) = setup_files()
drc_errors = 0
@@ -41,9 +42,9 @@ class library_lvs_test(openram_test):
# fail if the error count is not zero
self.assertEqual(drc_errors + lvs_errors, 0)
globals.end_openram()
openram.end_openram()
def setup_files():
gds_dir = OPTS.openram_tech + "/gds_lib"
sp_dir = OPTS.openram_tech + "/lvs_lib"
@@ -66,7 +67,7 @@ def setup_files():
tempnames[i] = re.sub('\.sp$', '', tempnames[i])
try:
from tech import blackbox_cells
from openram.tech import blackbox_cells
nameset = list(set(tempnames) - set(blackbox_cells))
except ImportError:
# remove duplicate base names
@@ -78,7 +79,7 @@ def setup_files():
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/03_contact_test.py
+11 -11
View File
@@ -1,27 +1,28 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class contact_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
from tech import active_stack, poly_stack, beol_stacks
from openram.tech import active_stack, poly_stack, beol_stacks
# Don't do active because of nwell contact rules
# Don't do metal3 because of min area rules
@@ -86,13 +87,12 @@ class contact_test(openram_test):
well_type="p")
self.local_drc_check(c)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/03_path_test.py
+12 -12
View File
@@ -1,27 +1,28 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
import debug
import openram
from openram import debug
from openram import OPTS
class path_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from base import wire_path
import tech
from base import design
openram.init_openram(config_file, is_unit_test=True)
from openram.base import wire_path
from openram import tech
from openram.base import design
min_space = 2 * tech.drc["minwidth_m1"]
layer_stack = ("m1")
@@ -86,13 +87,12 @@ class path_test(openram_test):
wire_path(w, layer_stack, position_list)
self.local_drc_check(w)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/03_ptx_1finger_nmos_test.py
+10 -10
View File
@@ -1,27 +1,27 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class ptx_1finger_nmos_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech
openram.init_openram(config_file, is_unit_test=True)
from openram import tech
debug.info(2, "Checking min size NMOS with 1 finger")
fet = factory.create(module_type="ptx",
@@ -30,12 +30,12 @@ class ptx_1finger_nmos_test(openram_test):
tx_type="nmos")
self.local_drc_check(fet)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/03_ptx_1finger_pmos_test.py
+11 -10
View File
@@ -1,26 +1,27 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class ptx_1finger_pmos_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech
openram.init_openram(config_file, is_unit_test=True)
from openram import tech
debug.info(2, "Checking min size PMOS with 1 finger")
fet = factory.create(module_type="ptx",
@@ -29,12 +30,12 @@ class ptx_1finger_pmos_test(openram_test):
tx_type="pmos")
self.local_drc_check(fet)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/03_ptx_3finger_nmos_test.py
+11 -10
View File
@@ -1,26 +1,27 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class ptx_3finger_nmos_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech
openram.init_openram(config_file, is_unit_test=True)
from openram import tech
debug.info(2, "Checking three fingers NMOS")
fet = factory.create(module_type="ptx",
@@ -32,12 +33,12 @@ class ptx_3finger_nmos_test(openram_test):
connect_poly=True)
self.local_drc_check(fet)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/03_ptx_3finger_pmos_test.py
+11 -10
View File
@@ -1,26 +1,27 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class ptx_3finger_pmos_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech
openram.init_openram(config_file, is_unit_test=True)
from openram import tech
debug.info(2, "Checking three fingers PMOS")
fet = factory.create(module_type="ptx",
@@ -32,12 +33,12 @@ class ptx_3finger_pmos_test(openram_test):
connect_poly=True)
self.local_drc_check(fet)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/03_ptx_4finger_nmos_test.py
+11 -10
View File
@@ -1,26 +1,27 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class ptx_4finger_nmos_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech
openram.init_openram(config_file, is_unit_test=True)
from openram import tech
debug.info(2, "Checking three fingers NMOS")
fet = factory.create(module_type="ptx",
@@ -32,12 +33,12 @@ class ptx_4finger_nmos_test(openram_test):
connect_poly=True)
self.local_drc_check(fet)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/03_ptx_4finger_pmos_test.py
+11 -10
View File
@@ -1,26 +1,27 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class ptx_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech
openram.init_openram(config_file, is_unit_test=True)
from openram import tech
debug.info(2, "Checking three fingers PMOS")
fet = factory.create(module_type="ptx",
@@ -32,12 +33,12 @@ class ptx_test(openram_test):
connect_poly=True)
self.local_drc_check(fet)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/03_ptx_no_contacts_test.py
+10 -10
View File
@@ -1,27 +1,27 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class ptx_no_contacts_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech
openram.init_openram(config_file, is_unit_test=True)
from openram import tech
debug.info(2, "Checking single finger no source/drain")
fet = factory.create(module_type="ptx",
@@ -49,12 +49,12 @@ class ptx_no_contacts_test(openram_test):
tx_type="nmos")
self.local_drc_check(fet)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/03_wire_test.py
+9 -10
View File
@@ -1,27 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys
import os
import globals
import openram
class wire_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from base import wire
import tech
from base import design
openram.init_openram(config_file, is_unit_test=True)
from openram.base import wire
from openram import tech
from openram.base import design
layer_stacks = [tech.poly_stack] + tech.beol_stacks
@@ -50,12 +49,12 @@ class wire_test(openram_test):
wire(w, layer_stack, position_list)
self.local_drc_check(w)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_and2_dec_test.py
+14 -13
View File
@@ -1,33 +1,33 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class and2_dec_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
global verify
import verify
openram.init_openram(config_file, is_unit_test=True)
#global verify
from openram import verify
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(2, "Testing and2_dec 1rw/1r gate")
a = factory.create(module_type="and2_dec")
@@ -36,17 +36,18 @@ class and2_dec_test(openram_test):
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(2, "Testing and2_dec 1rw gate")
a = factory.create(module_type="and2_dec")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_and3_dec_test.py
+14 -13
View File
@@ -1,33 +1,33 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class and3_dec_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
global verify
import verify
openram.init_openram(config_file, is_unit_test=True)
#global verify
from openram import verify
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(2, "Testing and3_dec 1rw/1r gate")
a = factory.create(module_type="and3_dec")
@@ -36,17 +36,18 @@ class and3_dec_test(openram_test):
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(2, "Testing and3_dec 1rw gate")
a = factory.create(module_type="and3_dec")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_and4_dec_test.py
+14 -13
View File
@@ -1,19 +1,19 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
# @unittest.skip("SKIPPING 04_and4_dec_test")
@@ -21,14 +21,14 @@ class and4_dec_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
global verify
import verify
openram.init_openram(config_file, is_unit_test=True)
#global verify
from openram import verify
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(2, "Testing and4_dec 1rw/1r gate")
a = factory.create(module_type="and4_dec")
@@ -37,17 +37,18 @@ class and4_dec_test(openram_test):
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(2, "Testing and4_dec 1rw gate")
a = factory.create(module_type="and4_dec")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_column_mux_1rw_1r_test.py
+11 -10
View File
@@ -1,31 +1,31 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class column_mux_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(2, "Checking column mux port 0")
tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
@@ -35,11 +35,12 @@ class column_mux_1rw_1r_test(openram_test):
tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_column_mux_pbitcell_test.py
+10 -11
View File
@@ -1,26 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class column_mux_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check single level column mux in multi-port
OPTS.bitcell = "pbitcell"
@@ -28,21 +28,20 @@ class column_mux_pbitcell_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
factory.reset()
debug.info(2, "Checking column mux for pbitcell (innermost connections)")
tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking column mux for pbitcell (outermost connections)")
tx = factory.create(module_type="column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_column_mux_test.py
+10 -9
View File
@@ -1,37 +1,38 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class column_mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check single level column mux in single port
debug.info(2, "Checking column mux")
tx = factory.create(module_type="column_mux", tx_size=8)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_dff_buf_test.py
+10 -9
View File
@@ -1,35 +1,36 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class dff_buf_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Testing dff_buf 4x 8x")
a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_dummy_pbitcell_test.py → compiler/tests/04_dummy_pbitcell_1rw1r1w_test.py
+12 -20
View File
@@ -1,51 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class replica_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from modules import dummy_pbitcell
openram.init_openram(config_file, is_unit_test=True)
from openram.modules import dummy_pbitcell
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
factory.reset()
debug.info(2, "Checking dummy bitcell using pbitcell (small cell)")
tx = dummy_pbitcell(name="rpbc")
self.local_check(tx)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
factory.reset()
debug.info(2, "Checking dummy bitcell using pbitcell (large cell)")
tx = dummy_pbitcell(name="rpbc")
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_dummy_pbitcell_1rw_test.py
Executable
+43
View File
@@ -0,0 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class dummy_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
from openram.modules import dummy_pbitcell
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
debug.info(2, "Checking dummy bitcell using pbitcell (small cell)")
tx = dummy_pbitcell(name="rpbc")
self.local_check(tx)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pand2_test.py
+12 -11
View File
@@ -1,39 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
import debug
import openram
from openram import debug
from openram import OPTS
class pand2_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
global verify
import verify
openram.init_openram(config_file, is_unit_test=True)
#global verify
from openram import verify
from modules import pand2
from openram.modules import pand2
debug.info(2, "Testing pand2 gate 4x")
a = pand2(name="pand2x4", size=4)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pand3_test.py
+12 -11
View File
@@ -1,39 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
import debug
import openram
from openram import debug
from openram import OPTS
class pand3_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
global verify
import verify
openram.init_openram(config_file, is_unit_test=True)
#global verify
from openram import verify
from modules import pand3
from openram.modules import pand3
debug.info(2, "Testing pand3 gate 4x")
a = pand3(name="pand3x4", size=4)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pand4_test.py
+12 -11
View File
@@ -1,39 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
import debug
import openram
from openram import debug
from openram import OPTS
class pand4_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
global verify
import verify
openram.init_openram(config_file, is_unit_test=True)
#global verify
from openram import verify
from modules import pand4
from openram.modules import pand4
debug.info(2, "Testing pand4 gate 4x")
a = pand4(name="pand4x4", size=4)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pbitcell_test.py
+10 -20
View File
@@ -1,31 +1,31 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
import debug
from sram_factory import factory
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
#@unittest.skip("SKIPPING 04_pbitcell_test")
class pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports=1
OPTS.num_w_ports=1
OPTS.num_r_ports=1
factory.reset()
debug.info(2, "Bitcell with 1 of each port: read/write, write, and read")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@@ -33,7 +33,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=0
OPTS.num_w_ports=1
OPTS.num_r_ports=1
factory.reset()
debug.info(2, "Bitcell with 0 read/write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@@ -41,7 +40,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=1
OPTS.num_w_ports=0
OPTS.num_r_ports=1
factory.reset()
debug.info(2, "Bitcell with 0 write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@@ -49,7 +47,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=1
OPTS.num_w_ports=1
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@@ -57,7 +54,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=1
OPTS.num_w_ports=0
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@@ -65,7 +61,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=2
OPTS.num_w_ports=2
OPTS.num_r_ports=2
factory.reset()
debug.info(2, "Bitcell with 2 of each port: read/write, write, and read")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@@ -73,7 +68,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=0
OPTS.num_w_ports=2
OPTS.num_r_ports=2
factory.reset()
debug.info(2, "Bitcell with 0 read/write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@@ -81,7 +75,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=2
OPTS.num_w_ports=0
OPTS.num_r_ports=2
factory.reset()
debug.info(2, "Bitcell with 0 write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@@ -89,7 +82,6 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=2
OPTS.num_w_ports=2
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
@@ -97,18 +89,16 @@ class pbitcell_test(openram_test):
OPTS.num_rw_ports=2
OPTS.num_w_ports=0
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pbuf_dec_8x_test.py
+12 -10
View File
@@ -1,40 +1,42 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pbuf_dec_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(2, "Checking 8x size decoder buffer")
a = factory.create(module_type="pbuf_dec", size=8)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pbuf_test.py
+11 -9
View File
@@ -1,35 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pbuf_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Testing buffer 8x")
a = factory.create(module_type="pbuf", size=8)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pdriver_test.py
+11 -9
View File
@@ -1,25 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pdriver_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Testing inverter/buffer 4x 8x")
# a tests the error message for specifying conflicting conditions
@@ -41,11 +42,12 @@ class pdriver_test(openram_test):
f = factory.create(module_type="pdriver", fanout = 64, inverting = True)
self.local_check(f)
globals.end_openram()
openram.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pinv_100x_test.py
+10 -9
View File
@@ -1,36 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pinv_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Checking 100x inverter")
tx = factory.create(module_type="pinv", size=100)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pinv_10x_test.py
+10 -9
View File
@@ -1,36 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pinv_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Checking 8x inverter")
tx = factory.create(module_type="pinv", size=8)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pinv_1x_beta_test.py
+11 -9
View File
@@ -1,35 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pinv_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Checking 1x beta=3 size inverter")
tx = factory.create(module_type="pinv", size=1, beta=3)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pinv_1x_test.py
+11 -9
View File
@@ -1,35 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pinv_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Checking 1x size inverter")
tx = factory.create(module_type="pinv", size=1)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pinv_2x_test.py
+10 -9
View File
@@ -1,36 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pinv_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Checking 2x size inverter")
tx = factory.create(module_type="pinv", size=2)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pinv_dec_1x_test.py
+11 -10
View File
@@ -1,41 +1,42 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pinv_dec_1x_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(2, "Checking 1x size decoder inverter")
tx = factory.create(module_type="pinv_dec", size=1)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pinvbuf_test.py
+11 -9
View File
@@ -1,35 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pinvbuf_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Testing inverter/buffer 4x 8x")
a = factory.create(module_type="pinvbuf", size=8)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pnand2_test.py
+10 -9
View File
@@ -1,25 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pnand2_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Checking 2-input nand gate")
tx = factory.create(module_type="pnand2", size=1)
@@ -30,12 +31,12 @@ class pnand2_test(openram_test):
# # Only DRC because well contacts will fail LVS
# self.local_drc_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pnand3_test.py
+10 -9
View File
@@ -1,25 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pnand3_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Checking 3-input nand gate")
tx = factory.create(module_type="pnand3", size=1)
@@ -30,12 +31,12 @@ class pnand3_test(openram_test):
# # Only DRC because well contacts will fail LVS
# self.local_drc_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pnand4_test.py
+9 -9
View File
@@ -1,37 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pnand4_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Checking 4-input nand gate")
tx = factory.create(module_type="pnand4", size=1)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pnor2_test.py
+11 -9
View File
@@ -1,35 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class pnor2_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Checking 2-input nor gate")
tx = factory.create(module_type="pnor2", size=1)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_precharge_1rw_1r_test.py
+11 -11
View File
@@ -1,47 +1,47 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class precharge_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check precharge array in multi-port
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(2, "Checking precharge for 1rw1r port 0")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking precharge for 1rw1r port 1")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_precharge_pbitcell_test.py
+11 -12
View File
@@ -1,25 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class precharge_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check precharge in multi-port
OPTS.bitcell = "pbitcell"
@@ -27,26 +28,24 @@ class precharge_pbitcell_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
factory.reset()
debug.info(2, "Checking precharge for pbitcell (innermost connections)")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking precharge for pbitcell (innermost connections)")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking precharge for pbitcell (outermost connections)")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2")
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_precharge_test.py
+10 -9
View File
@@ -1,37 +1,38 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class precharge_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check precharge in single port
debug.info(2, "Checking precharge for handmade bitcell")
tx = factory.create(module_type="precharge", size=1)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_pwrite_driver_test.py
+11 -10
View File
@@ -1,36 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import header, openram_test
import sys
import os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
@unittest.skip("SKIPPING 04_pwrite_driver_test")
class pwrite_driver_test(openram_test):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
openram.init_openram("config_{0}".format(OPTS.tech_name), is_unit_test=True)
debug.info(2, "Checking 1x pwrite_driver")
tx = factory.create(module_type="pwrite_driver", size=1)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/04_replica_pbitcell_test.py → compiler/tests/04_replica_pbitcell_1rw1r1w_test.py
+12 -20
View File
@@ -1,51 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class replica_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from modules import replica_pbitcell
openram.init_openram(config_file, is_unit_test=True)
from openram.modules import replica_pbitcell
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
factory.reset()
debug.info(2, "Checking replica bitcell using pbitcell (small cell)")
tx = replica_pbitcell(name="rpbc")
self.local_check(tx)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
factory.reset()
debug.info(2, "Checking replica bitcell using pbitcell (large cell)")
tx = replica_pbitcell(name="rpbc")
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_replica_pbitcell_1rw_test.py
Executable
+43
View File
@@ -0,0 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class replica_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
from openram.modules import replica_pbitcell
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
debug.info(2, "Checking replica bitcell using pbitcell (small cell)")
tx = replica_pbitcell(name="rpbc")
self.local_check(tx)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/04_wordline_driver_test.py
+11 -10
View File
@@ -1,38 +1,39 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
#@unittest.skip("SKIPPING 04_driver_test")
class wordline_driver_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check wordline driver for single port
debug.info(2, "Checking driver")
tx = factory.create(module_type="wordline_driver", cols=8)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/05_bitcell_array_1rw_1r_test.py
+11 -10
View File
@@ -1,41 +1,42 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class bitcell_array_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(2, "Testing 2x2 array for cell_2port")
a = factory.create(module_type="bitcell_array", cols=2, rows=2)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/05_bitcell_array_test.py
+10 -9
View File
@@ -1,26 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class array_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Testing 8x8 array for 6t_cell")
@@ -34,11 +34,12 @@ class array_test(openram_test):
a = factory.create(module_type="bitcell_array", cols=8 + num_spare_cols, rows=8 + num_spare_rows)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/05_dummy_array_test.py
+11 -9
View File
@@ -1,23 +1,24 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class dummy_row_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Testing dummy row for 6t_cell")
a = factory.create(module_type="dummy_array", rows=1, cols=4)
@@ -27,11 +28,12 @@ class dummy_row_test(openram_test):
a = factory.create(module_type="dummy_array", rows=4, cols=1)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/05_pbitcell_array_test.py
+11 -9
View File
@@ -1,26 +1,27 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
#@unittest.skip("SKIPPING 05_pbitcell_array_test")
class pbitcell_array_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
OPTS.bitcell = "pbitcell"
@@ -46,11 +47,12 @@ class pbitcell_array_test(openram_test):
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_column_decoder_16row_test.py
+11 -10
View File
@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class column_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 2x4 and 2-input NAND decoder
debug.info(1, "Testing 16 row sample for column_decoder")
a = factory.create(module_type="column_decoder", col_addr_size=4)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py
+11 -10
View File
@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 2x4 and 2 x 3x8 and 3-input NAND with non-power-of-two
debug.info(1, "Testing 132 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=132)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_132row_test.py
+11 -10
View File
@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 2x4 and 2 x 3x8 and 3-input NAND with non-power-of-two
debug.info(1, "Testing 132 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=132)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py
+11 -10
View File
@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 2x4 and 2-input NAND decoder
debug.info(1, "Testing 16 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_16row_test.py
+11 -10
View File
@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 2x4 and 2-input NAND decoder
debug.info(1, "Testing 16 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py
+11 -10
View File
@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 2x4 and 2-input NAND decoder with non-power-of-two
debug.info(1, "Testing 17 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_17row_test.py
+11 -10
View File
@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 2x4 and 2-input NAND decoder with non-power-of-two
debug.info(1, "Testing 17 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py
+11 -10
View File
@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 2x4 with 3x8 and 2-input NAND decoder
debug.info(1, "Testing 32 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_32row_test.py
+11 -10
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@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 2x4 with 3x8 and 2-input NAND decoder
debug.info(1, "Testing 32 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py
+11 -10
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@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 2x4 and 2-input NAND decoder
debug.info(1, "Testing 4096 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=4096)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_4096row_test.py
+11 -10
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@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 2x4 and 2-input NAND decoder
debug.info(1, "Testing 4096 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=4096)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py
+11 -10
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@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 3 x 3x8 and 3-input NAND decoder
debug.info(1, "Testing 512 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_512row_test.py
+11 -10
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@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 3 x 3x8 and 3-input NAND decoder
debug.info(1, "Testing 512 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py
+11 -10
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@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 3 x 2x4 and 3-input NAND decoder
debug.info(1, "Testing 64 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=64)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_64row_test.py
+11 -10
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@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# Checks 3 x 2x4 and 3-input NAND decoder
debug.info(1, "Testing 64 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=64)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_decoder_pbitcell_test.py
+11 -15
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@@ -1,43 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_decoder_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check hierarchical decoder for multi-port
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
factory.reset()
debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
self.local_check(a)
factory.reset()
debug.info(1, "Testing 17 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
self.local_check(a)
factory.reset()
debug.info(1, "Testing 23 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=23)
self.local_check(a)
@@ -46,7 +43,6 @@ class hierarchical_decoder_pbitcell_test(openram_test):
a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
self.local_check(a)
factory.reset()
debug.info(1, "Testing 65 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=65)
self.local_check(a)
@@ -55,7 +51,6 @@ class hierarchical_decoder_pbitcell_test(openram_test):
a = factory.create(module_type="hierarchical_decoder", num_outputs=128)
self.local_check(a)
factory.reset()
debug.info(1, "Testing 341 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=341)
self.local_check(a)
@@ -64,11 +59,12 @@ class hierarchical_decoder_pbitcell_test(openram_test):
a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py
+11 -10
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@@ -1,41 +1,42 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_predecode2x4_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(1, "Testing sample for hierarchy_predecode2x4")
a = factory.create(module_type="hierarchical_predecode2x4")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py
+11 -10
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@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_predecode2x4_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# checking hierarchical precode 2x4 for multi-port
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
a = factory.create(module_type="hierarchical_predecode2x4")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_predecode2x4_test.py
+10 -9
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@@ -1,36 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_predecode2x4_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(1, "Testing sample for hierarchy_predecode2x4")
a = factory.create(module_type="hierarchical_predecode2x4")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py
+11 -10
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@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_predecode3x8_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# Use the 2 port cell since it is usually bigger/easier
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(1, "Testing sample for hierarchy_predecode3x8")
a = factory.create(module_type="hierarchical_predecode3x8")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py
+11 -10
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@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_predecode3x8_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# checking hierarchical precode 3x8 for multi-port
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
a = factory.create(module_type="hierarchical_predecode3x8")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_predecode3x8_test.py
+10 -9
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@@ -1,36 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_predecode3x8_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(1, "Testing sample for hierarchy_predecode3x8")
a = factory.create(module_type="hierarchical_predecode3x8")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_hierarchical_predecode4x16_test.py
+11 -10
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@@ -1,42 +1,43 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class hierarchical_predecode4x16_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# Use the 2 port cell since it is usually bigger/easier
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(1, "Testing sample for hierarchy_predecode4x16")
a = factory.create(module_type="hierarchical_predecode4x16")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/06_rom_decoder_test.py
Executable
+37
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@@ -0,0 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import unittest
from testutils import *
import sys, os
import openram
from openram import OPTS
from openram.sram_factory import factory
from openram import debug
class rom_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Testing 2x4 decoder for rom cell")
a = factory.create(module_type="rom_decoder", num_outputs=16, strap_spacing=4, fanout=16)
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py
+10 -10
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@@ -1,30 +1,30 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from testutils import *
import sys, os
from testutils import *
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class column_mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(1, "Testing sample for 16-way column_mux_array port 0")
a = factory.create(module_type="column_mux_array", columns=32, word_size=2, bitcell_bl="bl0", bitcell_br="br0")
@@ -34,12 +34,12 @@ class column_mux_test(openram_test):
a = factory.create(module_type="column_mux_array", columns=32, word_size=2, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/07_column_mux_array_16mux_test.py
+9 -9
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@@ -1,36 +1,36 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from testutils import *
import sys, os
from testutils import *
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class column_mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(1, "Testing sample for 16-way column_mux_array")
a = factory.create(module_type="column_mux_array", columns=64, word_size=4)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py
+10 -10
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@@ -1,30 +1,30 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from testutils import *
import sys, os
from testutils import *
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class column_mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(1, "Testing sample for 2-way column_mux_array port 0")
a = factory.create(module_type="column_mux_array", columns=8, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
@@ -34,12 +34,12 @@ class column_mux_test(openram_test):
a = factory.create(module_type="column_mux_array", columns=8, word_size=4, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/07_column_mux_array_2mux_test.py
+9 -9
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@@ -1,36 +1,36 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from testutils import *
import sys, os
from testutils import *
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class column_mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(1, "Testing sample for 2-way column_mux_array")
a = factory.create(module_type="column_mux_array", columns=16, word_size=8)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py
+10 -10
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@@ -1,30 +1,30 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from testutils import *
import sys, os
from testutils import *
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class column_mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(1, "Testing sample for 4-way column_mux_array port 0")
a = factory.create(module_type="column_mux_array", columns=8, word_size=2, bitcell_bl="bl0", bitcell_br="br0")
@@ -34,12 +34,12 @@ class column_mux_test(openram_test):
a = factory.create(module_type="column_mux_array", columns=8, word_size=2, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/07_column_mux_array_4mux_test.py
+9 -9
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@@ -1,36 +1,36 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from testutils import *
import sys, os
from testutils import *
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class column_mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(1, "Testing sample for 4-way column_mux_array")
a = factory.create(module_type="column_mux_array", columns=16, word_size=4)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py
+10 -10
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@@ -1,30 +1,30 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from testutils import *
import sys, os
from testutils import *
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class column_mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(1, "Testing sample for 8-way column_mux_array port 0")
a = factory.create(module_type="column_mux_array", columns=16, word_size=2, bitcell_bl="bl0", bitcell_br="br0")
@@ -34,12 +34,12 @@ class column_mux_test(openram_test):
a = factory.create(module_type="column_mux_array", columns=16, word_size=2, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/07_column_mux_array_8mux_test.py
+9 -9
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@@ -1,36 +1,36 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from testutils import *
import sys, os
from testutils import *
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class column_mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(1, "Testing sample for 8-way column_mux_array")
a = factory.create(module_type="column_mux_array", columns=32, word_size=4)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/07_column_mux_array_pbitcell_test.py
+9 -10
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@@ -1,25 +1,25 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
from testutils import *
import sys, os
from testutils import *
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import OPTS
from openram.sram_factory import factory
from openram import debug
class column_mux_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check single level column mux array in multi-port
OPTS.bitcell = "pbitcell"
@@ -27,7 +27,6 @@ class column_mux_pbitcell_test(openram_test):
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
factory.reset()
debug.info(1, "Testing sample for 2-way column_mux_array in multi-port")
a = factory.create(module_type="column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a)
@@ -44,12 +43,12 @@ class column_mux_pbitcell_test(openram_test):
a = factory.create(module_type="column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2", column_offset=3)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/07_rom_column_mux_array_test.py
Executable
+36
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@@ -0,0 +1,36 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class rom_column_mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
debug.info(1, "Testing sample for 2-way rom column_mux_array")
a = factory.create(module_type="rom_column_mux_array", columns=16, word_size=8)
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/08_precharge_array_1rw_1r_test.py
+11 -11
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@@ -1,34 +1,33 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class precharge_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check precharge array in multi-port
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
factory.reset()
debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell (port 0)")
pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(pc)
@@ -37,11 +36,12 @@ class precharge_1rw_1r_test(openram_test):
pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0", column_offset=1)
self.local_check(pc)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/08_precharge_array_test.py
+11 -9
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@@ -1,35 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class precharge_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Checking 3 column precharge")
pc = factory.create(module_type="precharge_array", columns=3)
self.local_check(pc)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/08_rom_decoder_buffer_array_test.py
Executable
+37
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@@ -0,0 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import unittest
from testutils import *
import sys, os
import openram
from openram import OPTS
from openram.sram_factory import factory
from openram import debug
class rom_decoder_buffer_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Testing 4 col decoder buffer for rom decoder")
a = factory.create(module_type="rom_address_control_array", cols=4)
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/08_rom_precharge_array_test.py
Executable
+37
View File
@@ -0,0 +1,37 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import unittest
from testutils import *
import sys, os
import openram
from openram import OPTS
from openram.sram_factory import factory
from openram import debug
class rom_precharge_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Testing precharge array for rom cell")
a = factory.create(module_type="rom_precharge_array", cols=4, strap_spacing=2)
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/08_wordline_buffer_array_test.py
+10 -9
View File
@@ -1,37 +1,38 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class wordline_buffer_array_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check wordline driver for single port
debug.info(2, "Checking driver")
tx = factory.create(module_type="wordline_buffer_array", rows=8, cols=32)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/08_wordline_driver_array_1rw_1r_test.py
+11 -10
View File
@@ -1,43 +1,44 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class wordline_driver_array_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# Use the 2 port cell since it is usually bigger/easier
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
# check wordline driver for single port
debug.info(2, "Checking driver")
tx = factory.create(module_type="wordline_driver_array", rows=8, cols=32)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/08_wordline_driver_array_pbitcell_test.py
+10 -10
View File
@@ -1,26 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class wordline_driver_array_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check wordline driver for multi-port
OPTS.bitcell = "pbitcell"
@@ -28,16 +28,16 @@ class wordline_driver_array_pbitcell_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Checking driver (multi-port case)")
tx = factory.create(module_type="wordline_driver_array", rows=8, cols=64)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/08_wordline_driver_array_test.py
+10 -9
View File
@@ -1,37 +1,38 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class wordline_driver_array_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check wordline driver for single port
debug.info(2, "Checking driver")
tx = factory.create(module_type="wordline_driver_array", rows=8, cols=32)
self.local_check(tx)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/09_sense_amp_array_1rw_1r_test.py
+11 -10
View File
@@ -1,31 +1,31 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class sense_amp_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1")
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1)
@@ -39,11 +39,12 @@ class sense_amp_test(openram_test):
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/09_sense_amp_array_pbitcell_test.py
+11 -10
View File
@@ -1,25 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys,os
import unittest
from testutils import *
import sys,os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class sense_amp_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
#check sense amp array for multi-port
OPTS.bitcell = "pbitcell"
@@ -27,7 +28,6 @@ class sense_amp_pbitcell_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
self.local_check(a)
@@ -36,11 +36,12 @@ class sense_amp_pbitcell_test(openram_test):
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/09_sense_amp_array_spare_cols_test.py
+11 -10
View File
@@ -1,25 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class sense_amp_array_spare_cols_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check sense amp array for single port
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 and num_spare_cols=3")
@@ -36,7 +37,6 @@ class sense_amp_array_spare_cols_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2, num_spare_cols=2 (multi-port case)")
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2, num_spare_cols=2)
self.local_check(a)
@@ -45,11 +45,12 @@ class sense_amp_array_spare_cols_test(openram_test):
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4, num_spare_cols=3)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/09_sense_amp_array_test.py
+11 -9
View File
@@ -1,25 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class sense_amp_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1")
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1)
@@ -33,11 +34,12 @@ class sense_amp_test(openram_test):
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/10_rom_wordline_driver_array_test.py
Executable
+38
View File
@@ -0,0 +1,38 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class wordline_driver_array_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
# check wordline driver for single port
debug.info(2, "Checking driver")
tx = factory.create(module_type="rom_wordline_driver_array", rows=8, fanout=32)
self.local_check(tx)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/10_write_driver_array_1rw_1r_test.py
+11 -10
View File
@@ -1,31 +1,31 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class write_driver_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
openram.setup_bitcell()
debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
@@ -35,11 +35,12 @@ class write_driver_test(openram_test):
a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/10_write_driver_array_pbitcell_test.py
+11 -10
View File
@@ -1,25 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class write_driver_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check write driver array for multi-port
OPTS.bitcell = "pbitcell"
@@ -27,7 +28,6 @@ class write_driver_pbitcell_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
self.local_check(a)
@@ -36,11 +36,12 @@ class write_driver_pbitcell_test(openram_test):
a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/10_write_driver_array_spare_cols_test.py
+11 -10
View File
@@ -1,25 +1,26 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2021 Regents of the University of California and The Board
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import sys, os
import globals
from globals import OPTS
from sram_factory import factory
import debug
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class write_driver_array_spare_cols_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
openram.init_openram(config_file, is_unit_test=True)
# check write driver array for single port
debug.info(2, "Testing write_driver_array for columns=8, word_size=8 and num_spare_cols=3")
@@ -36,7 +37,6 @@ class write_driver_array_spare_cols_test(openram_test):
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case and num_spare_cols=3")
a = factory.create(module_type="write_driver_array", columns=8, word_size=8, num_spare_cols=3)
self.local_check(a)
@@ -45,11 +45,12 @@ class write_driver_array_spare_cols_test(openram_test):
a = factory.create(module_type="write_driver_array", columns=16, word_size=8, num_spare_cols=3)
self.local_check(a)
globals.end_openram()
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())

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